[PATCH] D95189: [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf8f1b20e6b30: [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95189/new/

https://reviews.llvm.org/D95189

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1581,13 +1581,13 @@
 
 multiclass VPseudoTernaryW_VV {
   defvar constraint = "@earlyclobber $rd";
-  foreach m = MxList.m in
+  foreach m = MxList.m[0-5] in
     defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
 }
 
 multiclass VPseudoTernaryW_VX<bit IsFloat> {
   defvar constraint = "@earlyclobber $rd";
-  foreach m = MxList.m in
+  foreach m = MxList.m[0-5] in
     defm !if(IsFloat, "_VF", "_VX")  : VPseudoTernary<m.wvrclass,
                              !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>;
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95189.318400.patch
Type: text/x-patch
Size: 777 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210122/c5f780fd/attachment.bin>