[PATCH] D95146: [RISCV] Make v extension imply zvamo, zvlsseg

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

In D95146#2513028 <https://reviews.llvm.org/D95146#2513028>, @simoncook wrote:

> In D95146#2512871 <https://reviews.llvm.org/D95146#2512871>, @craig.topper wrote:
>
>> Doesn't this mean that if you only enable zvlsseg, you'll be able to use the instruction in that extension but not the vsetvli instruction that you need to program the VL register?
>
> @craig.topper To be honest, I'm not at all familiar with the v extension or any of the zv* extensions. I wrote this in response to D94931 <https://reviews.llvm.org/D94931> which says that V should imply zv* but not the other way around. Looking back now at D85069 <https://reviews.llvm.org/D85069> it looks there was some discussion suggesting which way around it should be, so it could be this patch is unnecessary and breaks stuff. Do you have any better understand of the vector spec as to which way round is correct?
>
> @kito-cheng Similarly, do you know if the correct order of implication/requirements is well defined somewhere. If there are gcc/binutils patches what does it do here?

Hmmmmm, I don't think the spec has well defined that, it's kind of vague in this part, I've argue with ISA guys for this, and then got  this change in spec <https://github.com/riscv/riscv-v-spec/commit/79783b481b5750c1797ae0440040cb3e65edb5db>.

So how about GCC/binutils, GNU toolchain using a weird work-around here, `v` implied `zvamo` and `zvlsseg`, and `zvamo`/`zvlsseg`/`zvqmacc` implied `v`...

@craig.topper that's good point, I create a issue on spec: https://github.com/riscv/riscv-v-spec/issues/626


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