[PATCH] D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics.
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 21 18:48:55 PST 2021
HsiangKai updated this revision to Diff 318392.
HsiangKai retitled this revision from "[RISCV] Implement vsxseg intrinsics." to "[RISCV] Implement vsoxseg/vsuxseg intrinsics.".
HsiangKai edited the summary of this revision.
HsiangKai added a comment.
- Update to v1.0.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D94940/new/
https://reviews.llvm.org/D94940
Files:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D94940.318392.patch
Type: text/x-patch
Size: 10474 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210122/9c367017/attachment.bin>
More information about the llvm-commits
mailing list