[PATCH] D95028: [RISCV] Add intrinsics for vector unordered indexed loads in RVV 1.0

[ShihPo Hung via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG976cf53cc7a5: [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 (authored by arcbbb).

Changed prior to commit:
  https://reviews.llvm.org/D95028?vs=317801&id=318387#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95028/new/

https://reviews.llvm.org/D95028

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

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