[PATCH] D94816: [P10] [Power PC] Exploiting new load rightmost vector element instructions.

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3940
+let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {
+// Little endian Power10 subtargets produce a shorter pattern but require a
+// COPY_TO_REGCLASS making a faux equivalent pattern, NoP10Vector predicate
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nit: End sentences with a period.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3941
+// Little endian Power10 subtargets produce a shorter pattern but require a
+// COPY_TO_REGCLASS making a faux equivalent pattern, NoP10Vector predicate
+// excludes these patterns from Power10 VSX subtargets
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Might be a silly question, but can you clarify the "faux equivalent pattern" part?
Also a small nit, maybe end the sentence here and start the next sentence with, "The NoP10Vector predicate..."


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Comment at: llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll:8
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s --check-prefix=CHECK-BE
+
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Add P9 run line, too?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94816/new/

https://reviews.llvm.org/D94816