[llvm] 4ab0f51 - Recommit "[RISCV] Legalize select when Zbt extension available"
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 21 12:11:16 PST 2021
Author: Michael Munday
Date: 2021-01-21T12:07:44-08:00
New Revision: 4ab0f51a7518332b8b7691915b5fdad4c1ed045f
URL: https://github.com/llvm/llvm-project/commit/4ab0f51a7518332b8b7691915b5fdad4c1ed045f
DIFF: https://github.com/llvm/llvm-project/commit/4ab0f51a7518332b8b7691915b5fdad4c1ed045f.diff
LOG: Recommit "[RISCV] Legalize select when Zbt extension available"
This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with
the polarity of some of the pattern corrected.
Original commit message:
The custom expansion of select operations in the RISC-V backend
interferes with the matching of cmov instructions. Legalizing
select when the Zbt extension is available solves that problem.
Reviewed By: luismarques, craig.topper
Differential Revision: https://reviews.llvm.org/D93767
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbb.ll
llvm/test/CodeGen/RISCV/rv32Zbbp.ll
llvm/test/CodeGen/RISCV/rv32Zbs.ll
llvm/test/CodeGen/RISCV/rv32Zbt.ll
llvm/test/CodeGen/RISCV/rv64Zbt.ll
llvm/test/CodeGen/RISCV/select-and.ll
llvm/test/CodeGen/RISCV/select-bare.ll
llvm/test/CodeGen/RISCV/select-cc.ll
llvm/test/CodeGen/RISCV/select-const.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
llvm/test/CodeGen/RISCV/select-or.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index abbdfd54e897..23923ddb8485 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -163,7 +163,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, XLenVT, Expand);
- setOperationAction(ISD::SELECT, XLenVT, Custom);
setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
@@ -250,11 +249,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtZbt()) {
setOperationAction(ISD::FSHL, XLenVT, Legal);
setOperationAction(ISD::FSHR, XLenVT, Legal);
+ setOperationAction(ISD::SELECT, XLenVT, Legal);
if (Subtarget.is64Bit()) {
setOperationAction(ISD::FSHL, MVT::i32, Custom);
setOperationAction(ISD::FSHR, MVT::i32, Custom);
}
+ } else {
+ setOperationAction(ISD::SELECT, XLenVT, Custom);
}
ISD::CondCode FPCCToExpand[] = {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 205f8e65e655..5773535e3a69 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -717,7 +717,23 @@ def : Pat<(rotl (riscv_grevi GPR:$rs1, (i32 24)), (i32 16)), (GREVI GPR:$rs1, 8)
let Predicates = [HasStdExtZbt] in {
def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(riscv_selectcc GPR:$rs2, (XLenVT 0), (XLenVT 17), GPR:$rs3, GPR:$rs1),
+def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
} // Predicates = [HasStdExtZbt]
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbb.ll b/llvm/test/CodeGen/RISCV/rv32Zbb.ll
index b95fcd5f5232..d32b5c4f407e 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbb.ll
@@ -60,14 +60,7 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: slo_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a3, a2, -32
; RV32IB-NEXT: not a0, a0
-; RV32IB-NEXT: bltz a3, .LBB1_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a2, zero
-; RV32IB-NEXT: sll a1, a0, a3
-; RV32IB-NEXT: j .LBB1_3
-; RV32IB-NEXT: .LBB1_2:
; RV32IB-NEXT: not a1, a1
; RV32IB-NEXT: sll a1, a1, a2
; RV32IB-NEXT: addi a3, zero, 31
@@ -75,10 +68,15 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
; RV32IB-NEXT: srli a4, a0, 1
; RV32IB-NEXT: srl a3, a4, a3
; RV32IB-NEXT: or a1, a1, a3
-; RV32IB-NEXT: sll a2, a0, a2
-; RV32IB-NEXT: .LBB1_3:
+; RV32IB-NEXT: addi a3, a2, -32
+; RV32IB-NEXT: sll a4, a0, a3
+; RV32IB-NEXT: slti a5, a3, 0
+; RV32IB-NEXT: cmov a1, a5, a1, a4
+; RV32IB-NEXT: sll a0, a0, a2
+; RV32IB-NEXT: srai a2, a3, 31
+; RV32IB-NEXT: and a0, a2, a0
; RV32IB-NEXT: not a1, a1
-; RV32IB-NEXT: not a0, a2
+; RV32IB-NEXT: not a0, a0
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: slo_i64:
@@ -163,14 +161,7 @@ define i64 @sro_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: sro_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a3, a2, -32
; RV32IB-NEXT: not a1, a1
-; RV32IB-NEXT: bltz a3, .LBB3_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a2, zero
-; RV32IB-NEXT: srl a0, a1, a3
-; RV32IB-NEXT: j .LBB3_3
-; RV32IB-NEXT: .LBB3_2:
; RV32IB-NEXT: not a0, a0
; RV32IB-NEXT: srl a0, a0, a2
; RV32IB-NEXT: addi a3, zero, 31
@@ -178,10 +169,15 @@ define i64 @sro_i64(i64 %a, i64 %b) nounwind {
; RV32IB-NEXT: slli a4, a1, 1
; RV32IB-NEXT: sll a3, a4, a3
; RV32IB-NEXT: or a0, a0, a3
-; RV32IB-NEXT: srl a2, a1, a2
-; RV32IB-NEXT: .LBB3_3:
+; RV32IB-NEXT: addi a3, a2, -32
+; RV32IB-NEXT: srl a4, a1, a3
+; RV32IB-NEXT: slti a5, a3, 0
+; RV32IB-NEXT: cmov a0, a5, a0, a4
+; RV32IB-NEXT: srl a1, a1, a2
+; RV32IB-NEXT: srai a2, a3, 31
+; RV32IB-NEXT: and a1, a2, a1
; RV32IB-NEXT: not a0, a0
-; RV32IB-NEXT: not a1, a2
+; RV32IB-NEXT: not a1, a1
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: sro_i64:
@@ -466,14 +462,10 @@ define i64 @ctlz_i64(i64 %a) nounwind {
;
; RV32IB-LABEL: ctlz_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bnez a1, .LBB9_2
-; RV32IB-NEXT: # %bb.1:
+; RV32IB-NEXT: clz a2, a1
; RV32IB-NEXT: clz a0, a0
; RV32IB-NEXT: addi a0, a0, 32
-; RV32IB-NEXT: mv a1, zero
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB9_2:
-; RV32IB-NEXT: clz a0, a1
+; RV32IB-NEXT: cmov a0, a1, a2, a0
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
@@ -623,14 +615,10 @@ define i64 @cttz_i64(i64 %a) nounwind {
;
; RV32IB-LABEL: cttz_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bnez a0, .LBB11_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: ctz a0, a1
-; RV32IB-NEXT: addi a0, a0, 32
-; RV32IB-NEXT: mv a1, zero
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB11_2:
-; RV32IB-NEXT: ctz a0, a0
+; RV32IB-NEXT: ctz a2, a0
+; RV32IB-NEXT: ctz a1, a1
+; RV32IB-NEXT: addi a1, a1, 32
+; RV32IB-NEXT: cmov a0, a0, a2, a1
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
@@ -910,18 +898,11 @@ define i64 @min_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: min_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: mv a4, a0
-; RV32IB-NEXT: bge a1, a3, .LBB19_3
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: beq a1, a3, .LBB19_4
-; RV32IB-NEXT: .LBB19_2:
-; RV32IB-NEXT: min a1, a1, a3
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB19_3:
-; RV32IB-NEXT: mv a0, a2
-; RV32IB-NEXT: bne a1, a3, .LBB19_2
-; RV32IB-NEXT: .LBB19_4:
-; RV32IB-NEXT: minu a0, a4, a2
+; RV32IB-NEXT: slt a4, a1, a3
+; RV32IB-NEXT: cmov a4, a4, a0, a2
+; RV32IB-NEXT: minu a0, a0, a2
+; RV32IB-NEXT: xor a2, a1, a3
+; RV32IB-NEXT: cmov a0, a2, a4, a0
; RV32IB-NEXT: min a1, a1, a3
; RV32IB-NEXT: ret
;
@@ -993,18 +974,11 @@ define i64 @max_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: max_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: mv a4, a0
-; RV32IB-NEXT: bge a3, a1, .LBB21_3
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: beq a1, a3, .LBB21_4
-; RV32IB-NEXT: .LBB21_2:
-; RV32IB-NEXT: max a1, a1, a3
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB21_3:
-; RV32IB-NEXT: mv a0, a2
-; RV32IB-NEXT: bne a1, a3, .LBB21_2
-; RV32IB-NEXT: .LBB21_4:
-; RV32IB-NEXT: maxu a0, a4, a2
+; RV32IB-NEXT: slt a4, a3, a1
+; RV32IB-NEXT: cmov a4, a4, a0, a2
+; RV32IB-NEXT: maxu a0, a0, a2
+; RV32IB-NEXT: xor a2, a1, a3
+; RV32IB-NEXT: cmov a0, a2, a4, a0
; RV32IB-NEXT: max a1, a1, a3
; RV32IB-NEXT: ret
;
@@ -1076,18 +1050,11 @@ define i64 @minu_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: minu_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: mv a4, a0
-; RV32IB-NEXT: bgeu a1, a3, .LBB23_3
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: beq a1, a3, .LBB23_4
-; RV32IB-NEXT: .LBB23_2:
-; RV32IB-NEXT: minu a1, a1, a3
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB23_3:
-; RV32IB-NEXT: mv a0, a2
-; RV32IB-NEXT: bne a1, a3, .LBB23_2
-; RV32IB-NEXT: .LBB23_4:
-; RV32IB-NEXT: minu a0, a4, a2
+; RV32IB-NEXT: sltu a4, a1, a3
+; RV32IB-NEXT: cmov a4, a4, a0, a2
+; RV32IB-NEXT: minu a0, a0, a2
+; RV32IB-NEXT: xor a2, a1, a3
+; RV32IB-NEXT: cmov a0, a2, a4, a0
; RV32IB-NEXT: minu a1, a1, a3
; RV32IB-NEXT: ret
;
@@ -1159,18 +1126,11 @@ define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: maxu_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: mv a4, a0
-; RV32IB-NEXT: bgeu a3, a1, .LBB25_3
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: beq a1, a3, .LBB25_4
-; RV32IB-NEXT: .LBB25_2:
-; RV32IB-NEXT: maxu a1, a1, a3
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB25_3:
-; RV32IB-NEXT: mv a0, a2
-; RV32IB-NEXT: bne a1, a3, .LBB25_2
-; RV32IB-NEXT: .LBB25_4:
-; RV32IB-NEXT: maxu a0, a4, a2
+; RV32IB-NEXT: sltu a4, a3, a1
+; RV32IB-NEXT: cmov a4, a4, a0, a2
+; RV32IB-NEXT: maxu a0, a0, a2
+; RV32IB-NEXT: xor a2, a1, a3
+; RV32IB-NEXT: cmov a0, a2, a4, a0
; RV32IB-NEXT: maxu a1, a1, a3
; RV32IB-NEXT: ret
;
@@ -1236,13 +1196,14 @@ define i64 @abs_i64(i64 %x) {
;
; RV32IB-LABEL: abs_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bgez a1, .LBB27_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: snez a2, a0
+; RV32IB-NEXT: neg a2, a0
+; RV32IB-NEXT: slti a3, a1, 0
+; RV32IB-NEXT: cmov a2, a3, a2, a0
+; RV32IB-NEXT: snez a0, a0
+; RV32IB-NEXT: add a0, a1, a0
; RV32IB-NEXT: neg a0, a0
-; RV32IB-NEXT: add a1, a1, a2
-; RV32IB-NEXT: neg a1, a1
-; RV32IB-NEXT: .LBB27_2:
+; RV32IB-NEXT: cmov a1, a3, a0, a1
+; RV32IB-NEXT: mv a0, a2
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: abs_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbbp.ll b/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
index 0ae6d757287f..674ca5146b19 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
@@ -264,48 +264,37 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: rol_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: andi a3, a2, 63
-; RV32IB-NEXT: addi t1, a3, -32
+; RV32IB-NEXT: sll a7, a1, a2
+; RV32IB-NEXT: andi a4, a2, 63
; RV32IB-NEXT: addi a6, zero, 31
-; RV32IB-NEXT: bltz t1, .LBB7_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: sll a7, a0, t1
-; RV32IB-NEXT: j .LBB7_3
-; RV32IB-NEXT: .LBB7_2:
-; RV32IB-NEXT: sll a4, a1, a2
-; RV32IB-NEXT: sub a3, a6, a3
-; RV32IB-NEXT: srli a5, a0, 1
-; RV32IB-NEXT: srl a3, a5, a3
-; RV32IB-NEXT: or a7, a4, a3
-; RV32IB-NEXT: .LBB7_3:
-; RV32IB-NEXT: neg a4, a2
-; RV32IB-NEXT: andi a5, a4, 63
-; RV32IB-NEXT: addi a3, a5, -32
-; RV32IB-NEXT: bltz a3, .LBB7_7
-; RV32IB-NEXT: # %bb.4:
-; RV32IB-NEXT: mv t0, zero
-; RV32IB-NEXT: bgez a3, .LBB7_8
-; RV32IB-NEXT: .LBB7_5:
-; RV32IB-NEXT: srl a3, a0, a4
-; RV32IB-NEXT: sub a4, a6, a5
-; RV32IB-NEXT: slli a1, a1, 1
-; RV32IB-NEXT: sll a1, a1, a4
-; RV32IB-NEXT: or a4, a3, a1
-; RV32IB-NEXT: or a1, a7, t0
-; RV32IB-NEXT: bgez t1, .LBB7_9
-; RV32IB-NEXT: .LBB7_6:
+; RV32IB-NEXT: sub a5, a6, a4
+; RV32IB-NEXT: srli a3, a0, 1
+; RV32IB-NEXT: srl a3, a3, a5
+; RV32IB-NEXT: or a7, a7, a3
+; RV32IB-NEXT: addi t1, a4, -32
+; RV32IB-NEXT: sll a5, a0, t1
+; RV32IB-NEXT: slti a3, t1, 0
+; RV32IB-NEXT: cmov a7, a3, a7, a5
+; RV32IB-NEXT: neg a5, a2
+; RV32IB-NEXT: srl t0, a1, a5
+; RV32IB-NEXT: andi t2, a5, 63
+; RV32IB-NEXT: addi a4, t2, -32
+; RV32IB-NEXT: srai a3, a4, 31
+; RV32IB-NEXT: and a3, a3, t0
+; RV32IB-NEXT: or a7, a7, a3
+; RV32IB-NEXT: srl t0, a0, a5
+; RV32IB-NEXT: sub a5, a6, t2
+; RV32IB-NEXT: slli a3, a1, 1
+; RV32IB-NEXT: sll a3, a3, a5
+; RV32IB-NEXT: or a3, t0, a3
+; RV32IB-NEXT: srl a1, a1, a4
+; RV32IB-NEXT: slti a4, a4, 0
+; RV32IB-NEXT: cmov a1, a4, a3, a1
; RV32IB-NEXT: sll a0, a0, a2
-; RV32IB-NEXT: or a0, a0, a4
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB7_7:
-; RV32IB-NEXT: srl t0, a1, a4
-; RV32IB-NEXT: bltz a3, .LBB7_5
-; RV32IB-NEXT: .LBB7_8:
-; RV32IB-NEXT: srl a4, a1, a3
-; RV32IB-NEXT: or a1, a7, t0
-; RV32IB-NEXT: bltz t1, .LBB7_6
-; RV32IB-NEXT: .LBB7_9:
-; RV32IB-NEXT: or a0, zero, a4
+; RV32IB-NEXT: srai a2, t1, 31
+; RV32IB-NEXT: and a0, a2, a0
+; RV32IB-NEXT: or a0, a0, a1
+; RV32IB-NEXT: mv a1, a7
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: rol_i64:
@@ -488,48 +477,37 @@ define i64 @ror_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: ror_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: andi a3, a2, 63
-; RV32IB-NEXT: addi t1, a3, -32
+; RV32IB-NEXT: srl a7, a0, a2
+; RV32IB-NEXT: andi a4, a2, 63
; RV32IB-NEXT: addi a6, zero, 31
-; RV32IB-NEXT: bltz t1, .LBB9_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: srl a7, a1, t1
-; RV32IB-NEXT: j .LBB9_3
-; RV32IB-NEXT: .LBB9_2:
-; RV32IB-NEXT: srl a4, a0, a2
-; RV32IB-NEXT: sub a3, a6, a3
-; RV32IB-NEXT: slli a5, a1, 1
-; RV32IB-NEXT: sll a3, a5, a3
-; RV32IB-NEXT: or a7, a4, a3
-; RV32IB-NEXT: .LBB9_3:
-; RV32IB-NEXT: neg a4, a2
-; RV32IB-NEXT: andi a5, a4, 63
-; RV32IB-NEXT: addi a3, a5, -32
-; RV32IB-NEXT: bltz a3, .LBB9_7
-; RV32IB-NEXT: # %bb.4:
-; RV32IB-NEXT: mv t0, zero
-; RV32IB-NEXT: bgez a3, .LBB9_8
-; RV32IB-NEXT: .LBB9_5:
-; RV32IB-NEXT: sll a3, a1, a4
-; RV32IB-NEXT: sub a4, a6, a5
-; RV32IB-NEXT: srli a0, a0, 1
-; RV32IB-NEXT: srl a0, a0, a4
-; RV32IB-NEXT: or a4, a3, a0
-; RV32IB-NEXT: or a0, a7, t0
-; RV32IB-NEXT: bgez t1, .LBB9_9
-; RV32IB-NEXT: .LBB9_6:
+; RV32IB-NEXT: sub a5, a6, a4
+; RV32IB-NEXT: slli a3, a1, 1
+; RV32IB-NEXT: sll a3, a3, a5
+; RV32IB-NEXT: or a7, a7, a3
+; RV32IB-NEXT: addi t1, a4, -32
+; RV32IB-NEXT: srl a5, a1, t1
+; RV32IB-NEXT: slti a3, t1, 0
+; RV32IB-NEXT: cmov a7, a3, a7, a5
+; RV32IB-NEXT: neg a5, a2
+; RV32IB-NEXT: sll t0, a0, a5
+; RV32IB-NEXT: andi t2, a5, 63
+; RV32IB-NEXT: addi a4, t2, -32
+; RV32IB-NEXT: srai a3, a4, 31
+; RV32IB-NEXT: and a3, a3, t0
+; RV32IB-NEXT: or a7, a7, a3
+; RV32IB-NEXT: sll t0, a1, a5
+; RV32IB-NEXT: sub a5, a6, t2
+; RV32IB-NEXT: srli a3, a0, 1
+; RV32IB-NEXT: srl a3, a3, a5
+; RV32IB-NEXT: or a3, t0, a3
+; RV32IB-NEXT: sll a0, a0, a4
+; RV32IB-NEXT: slti a4, a4, 0
+; RV32IB-NEXT: cmov a0, a4, a3, a0
; RV32IB-NEXT: srl a1, a1, a2
-; RV32IB-NEXT: or a1, a1, a4
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB9_7:
-; RV32IB-NEXT: sll t0, a0, a4
-; RV32IB-NEXT: bltz a3, .LBB9_5
-; RV32IB-NEXT: .LBB9_8:
-; RV32IB-NEXT: sll a4, a0, a3
-; RV32IB-NEXT: or a0, a7, t0
-; RV32IB-NEXT: bltz t1, .LBB9_6
-; RV32IB-NEXT: .LBB9_9:
-; RV32IB-NEXT: or a1, zero, a4
+; RV32IB-NEXT: srai a2, t1, 31
+; RV32IB-NEXT: and a1, a2, a1
+; RV32IB-NEXT: or a1, a1, a0
+; RV32IB-NEXT: mv a0, a7
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: ror_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbs.ll b/llvm/test/CodeGen/RISCV/rv32Zbs.ll
index ebe33744725a..fc0efd63a45c 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbs.ll
@@ -80,17 +80,14 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
; RV32IB: # %bb.0:
; RV32IB-NEXT: andi a3, a2, 63
; RV32IB-NEXT: addi a3, a3, -32
-; RV32IB-NEXT: bltz a3, .LBB2_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a2, zero
-; RV32IB-NEXT: sbset a3, zero, a3
-; RV32IB-NEXT: j .LBB2_3
-; RV32IB-NEXT: .LBB2_2:
-; RV32IB-NEXT: mv a3, zero
+; RV32IB-NEXT: sbset a4, zero, a3
+; RV32IB-NEXT: slti a5, a3, 0
+; RV32IB-NEXT: cmov a4, a5, zero, a4
; RV32IB-NEXT: sbset a2, zero, a2
-; RV32IB-NEXT: .LBB2_3:
+; RV32IB-NEXT: srai a3, a3, 31
+; RV32IB-NEXT: and a2, a3, a2
+; RV32IB-NEXT: andn a1, a1, a4
; RV32IB-NEXT: andn a0, a0, a2
-; RV32IB-NEXT: andn a1, a1, a3
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: sbclr_i64:
@@ -239,15 +236,13 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
;
; RV32IB-LABEL: sbset_i64_zero:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a1, a0, -32
-; RV32IB-NEXT: bltz a1, .LBB7_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a0, zero
-; RV32IB-NEXT: sbset a1, zero, a1
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB7_2:
-; RV32IB-NEXT: mv a1, zero
+; RV32IB-NEXT: addi a2, a0, -32
+; RV32IB-NEXT: sbset a1, zero, a2
+; RV32IB-NEXT: slti a3, a2, 0
+; RV32IB-NEXT: cmov a1, a3, zero, a1
; RV32IB-NEXT: sbset a0, zero, a0
+; RV32IB-NEXT: srai a2, a2, 31
+; RV32IB-NEXT: and a0, a2, a0
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: sbset_i64_zero:
@@ -398,20 +393,17 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
;
; RV32IB-LABEL: sbext_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: andi a3, a2, 63
-; RV32IB-NEXT: addi a4, a3, -32
-; RV32IB-NEXT: bltz a4, .LBB12_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: srl a0, a1, a4
-; RV32IB-NEXT: j .LBB12_3
-; RV32IB-NEXT: .LBB12_2:
; RV32IB-NEXT: srl a0, a0, a2
-; RV32IB-NEXT: addi a2, zero, 31
-; RV32IB-NEXT: sub a2, a2, a3
-; RV32IB-NEXT: slli a1, a1, 1
-; RV32IB-NEXT: sll a1, a1, a2
-; RV32IB-NEXT: or a0, a0, a1
-; RV32IB-NEXT: .LBB12_3:
+; RV32IB-NEXT: andi a2, a2, 63
+; RV32IB-NEXT: addi a3, zero, 31
+; RV32IB-NEXT: sub a3, a3, a2
+; RV32IB-NEXT: slli a4, a1, 1
+; RV32IB-NEXT: sll a3, a4, a3
+; RV32IB-NEXT: or a0, a0, a3
+; RV32IB-NEXT: addi a2, a2, -32
+; RV32IB-NEXT: srl a1, a1, a2
+; RV32IB-NEXT: slti a2, a2, 0
+; RV32IB-NEXT: cmov a0, a2, a0, a1
; RV32IB-NEXT: andi a0, a0, 1
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbt.ll b/llvm/test/CodeGen/RISCV/rv32Zbt.ll
index 279c39344b7d..24616cc7d41d 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbt.ll
@@ -97,18 +97,14 @@ define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
;
; RV32IB-LABEL: cmov_sle_i32:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bge a2, a1, .LBB3_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a0, a3
-; RV32IB-NEXT: .LBB3_2:
+; RV32IB-NEXT: slt a1, a2, a1
+; RV32IB-NEXT: cmov a0, a1, a3, a0
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_sle_i32:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: bge a2, a1, .LBB3_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB3_2:
+; RV32IBT-NEXT: slt a1, a2, a1
+; RV32IBT-NEXT: cmov a0, a1, a3, a0
; RV32IBT-NEXT: ret
%tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -126,18 +122,14 @@ define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
;
; RV32IB-LABEL: cmov_sge_i32:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bge a1, a2, .LBB4_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a0, a3
-; RV32IB-NEXT: .LBB4_2:
+; RV32IB-NEXT: slt a1, a1, a2
+; RV32IB-NEXT: cmov a0, a1, a3, a0
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_sge_i32:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: bge a1, a2, .LBB4_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB4_2:
+; RV32IBT-NEXT: slt a1, a1, a2
+; RV32IBT-NEXT: cmov a0, a1, a3, a0
; RV32IBT-NEXT: ret
%tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -155,18 +147,14 @@ define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
;
; RV32IB-LABEL: cmov_ule_i32:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bgeu a2, a1, .LBB5_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a0, a3
-; RV32IB-NEXT: .LBB5_2:
+; RV32IB-NEXT: sltu a1, a2, a1
+; RV32IB-NEXT: cmov a0, a1, a3, a0
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_ule_i32:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: bgeu a2, a1, .LBB5_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB5_2:
+; RV32IBT-NEXT: sltu a1, a2, a1
+; RV32IBT-NEXT: cmov a0, a1, a3, a0
; RV32IBT-NEXT: ret
%tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -184,18 +172,14 @@ define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
;
; RV32IB-LABEL: cmov_uge_i32:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: bgeu a1, a2, .LBB6_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: mv a0, a3
-; RV32IB-NEXT: .LBB6_2:
+; RV32IB-NEXT: sltu a1, a1, a2
+; RV32IB-NEXT: cmov a0, a1, a3, a0
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_uge_i32:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: bgeu a1, a2, .LBB6_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB6_2:
+; RV32IBT-NEXT: sltu a1, a1, a2
+; RV32IBT-NEXT: cmov a0, a1, a3, a0
; RV32IBT-NEXT: ret
%tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -254,38 +238,26 @@ define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV32IB-LABEL: cmov_sle_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: beq a3, a5, .LBB8_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: slt a2, a5, a3
-; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: beqz a2, .LBB8_3
-; RV32IB-NEXT: j .LBB8_4
-; RV32IB-NEXT: .LBB8_2:
+; RV32IB-NEXT: xor t0, a3, a5
; RV32IB-NEXT: sltu a2, a4, a2
; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: bnez a2, .LBB8_4
-; RV32IB-NEXT: .LBB8_3:
-; RV32IB-NEXT: mv a0, a6
-; RV32IB-NEXT: mv a1, a7
-; RV32IB-NEXT: .LBB8_4:
+; RV32IB-NEXT: slt a3, a5, a3
+; RV32IB-NEXT: xori a3, a3, 1
+; RV32IB-NEXT: cmov a2, t0, a3, a2
+; RV32IB-NEXT: cmov a0, a2, a0, a6
+; RV32IB-NEXT: cmov a1, a2, a1, a7
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_sle_i64:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: beq a3, a5, .LBB8_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: slt a2, a5, a3
-; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: beqz a2, .LBB8_3
-; RV32IBT-NEXT: j .LBB8_4
-; RV32IBT-NEXT: .LBB8_2:
+; RV32IBT-NEXT: xor t0, a3, a5
; RV32IBT-NEXT: sltu a2, a4, a2
; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: bnez a2, .LBB8_4
-; RV32IBT-NEXT: .LBB8_3:
-; RV32IBT-NEXT: mv a0, a6
-; RV32IBT-NEXT: mv a1, a7
-; RV32IBT-NEXT: .LBB8_4:
+; RV32IBT-NEXT: slt a3, a5, a3
+; RV32IBT-NEXT: xori a3, a3, 1
+; RV32IBT-NEXT: cmov a2, t0, a3, a2
+; RV32IBT-NEXT: cmov a0, a2, a0, a6
+; RV32IBT-NEXT: cmov a1, a2, a1, a7
; RV32IBT-NEXT: ret
%tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -313,38 +285,26 @@ define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV32IB-LABEL: cmov_sge_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: beq a3, a5, .LBB9_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: slt a2, a3, a5
-; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: beqz a2, .LBB9_3
-; RV32IB-NEXT: j .LBB9_4
-; RV32IB-NEXT: .LBB9_2:
+; RV32IB-NEXT: xor t0, a3, a5
; RV32IB-NEXT: sltu a2, a2, a4
; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: bnez a2, .LBB9_4
-; RV32IB-NEXT: .LBB9_3:
-; RV32IB-NEXT: mv a0, a6
-; RV32IB-NEXT: mv a1, a7
-; RV32IB-NEXT: .LBB9_4:
+; RV32IB-NEXT: slt a3, a3, a5
+; RV32IB-NEXT: xori a3, a3, 1
+; RV32IB-NEXT: cmov a2, t0, a3, a2
+; RV32IB-NEXT: cmov a0, a2, a0, a6
+; RV32IB-NEXT: cmov a1, a2, a1, a7
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_sge_i64:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: beq a3, a5, .LBB9_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: slt a2, a3, a5
-; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: beqz a2, .LBB9_3
-; RV32IBT-NEXT: j .LBB9_4
-; RV32IBT-NEXT: .LBB9_2:
+; RV32IBT-NEXT: xor t0, a3, a5
; RV32IBT-NEXT: sltu a2, a2, a4
; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: bnez a2, .LBB9_4
-; RV32IBT-NEXT: .LBB9_3:
-; RV32IBT-NEXT: mv a0, a6
-; RV32IBT-NEXT: mv a1, a7
-; RV32IBT-NEXT: .LBB9_4:
+; RV32IBT-NEXT: slt a3, a3, a5
+; RV32IBT-NEXT: xori a3, a3, 1
+; RV32IBT-NEXT: cmov a2, t0, a3, a2
+; RV32IBT-NEXT: cmov a0, a2, a0, a6
+; RV32IBT-NEXT: cmov a1, a2, a1, a7
; RV32IBT-NEXT: ret
%tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -372,38 +332,26 @@ define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV32IB-LABEL: cmov_ule_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: beq a3, a5, .LBB10_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: sltu a2, a5, a3
-; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: beqz a2, .LBB10_3
-; RV32IB-NEXT: j .LBB10_4
-; RV32IB-NEXT: .LBB10_2:
+; RV32IB-NEXT: xor t0, a3, a5
; RV32IB-NEXT: sltu a2, a4, a2
; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: bnez a2, .LBB10_4
-; RV32IB-NEXT: .LBB10_3:
-; RV32IB-NEXT: mv a0, a6
-; RV32IB-NEXT: mv a1, a7
-; RV32IB-NEXT: .LBB10_4:
+; RV32IB-NEXT: sltu a3, a5, a3
+; RV32IB-NEXT: xori a3, a3, 1
+; RV32IB-NEXT: cmov a2, t0, a3, a2
+; RV32IB-NEXT: cmov a0, a2, a0, a6
+; RV32IB-NEXT: cmov a1, a2, a1, a7
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_ule_i64:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: beq a3, a5, .LBB10_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: sltu a2, a5, a3
-; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: beqz a2, .LBB10_3
-; RV32IBT-NEXT: j .LBB10_4
-; RV32IBT-NEXT: .LBB10_2:
+; RV32IBT-NEXT: xor t0, a3, a5
; RV32IBT-NEXT: sltu a2, a4, a2
; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: bnez a2, .LBB10_4
-; RV32IBT-NEXT: .LBB10_3:
-; RV32IBT-NEXT: mv a0, a6
-; RV32IBT-NEXT: mv a1, a7
-; RV32IBT-NEXT: .LBB10_4:
+; RV32IBT-NEXT: sltu a3, a5, a3
+; RV32IBT-NEXT: xori a3, a3, 1
+; RV32IBT-NEXT: cmov a2, t0, a3, a2
+; RV32IBT-NEXT: cmov a0, a2, a0, a6
+; RV32IBT-NEXT: cmov a1, a2, a1, a7
; RV32IBT-NEXT: ret
%tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -431,38 +379,26 @@ define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV32IB-LABEL: cmov_uge_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: beq a3, a5, .LBB11_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: sltu a2, a3, a5
-; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: beqz a2, .LBB11_3
-; RV32IB-NEXT: j .LBB11_4
-; RV32IB-NEXT: .LBB11_2:
+; RV32IB-NEXT: xor t0, a3, a5
; RV32IB-NEXT: sltu a2, a2, a4
; RV32IB-NEXT: xori a2, a2, 1
-; RV32IB-NEXT: bnez a2, .LBB11_4
-; RV32IB-NEXT: .LBB11_3:
-; RV32IB-NEXT: mv a0, a6
-; RV32IB-NEXT: mv a1, a7
-; RV32IB-NEXT: .LBB11_4:
+; RV32IB-NEXT: sltu a3, a3, a5
+; RV32IB-NEXT: xori a3, a3, 1
+; RV32IB-NEXT: cmov a2, t0, a3, a2
+; RV32IB-NEXT: cmov a0, a2, a0, a6
+; RV32IB-NEXT: cmov a1, a2, a1, a7
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: cmov_uge_i64:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: beq a3, a5, .LBB11_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: sltu a2, a3, a5
-; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: beqz a2, .LBB11_3
-; RV32IBT-NEXT: j .LBB11_4
-; RV32IBT-NEXT: .LBB11_2:
+; RV32IBT-NEXT: xor t0, a3, a5
; RV32IBT-NEXT: sltu a2, a2, a4
; RV32IBT-NEXT: xori a2, a2, 1
-; RV32IBT-NEXT: bnez a2, .LBB11_4
-; RV32IBT-NEXT: .LBB11_3:
-; RV32IBT-NEXT: mv a0, a6
-; RV32IBT-NEXT: mv a1, a7
-; RV32IBT-NEXT: .LBB11_4:
+; RV32IBT-NEXT: sltu a3, a3, a5
+; RV32IBT-NEXT: xori a3, a3, 1
+; RV32IBT-NEXT: cmov a2, t0, a3, a2
+; RV32IBT-NEXT: cmov a0, a2, a0, a6
+; RV32IBT-NEXT: cmov a1, a2, a1, a7
; RV32IBT-NEXT: ret
%tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -557,99 +493,75 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
;
; RV32IB-LABEL: fshl_i64:
; RV32IB: # %bb.0:
+; RV32IB-NEXT: sll a7, a1, a4
; RV32IB-NEXT: andi a5, a4, 63
-; RV32IB-NEXT: addi t2, a5, -32
; RV32IB-NEXT: addi a6, zero, 31
-; RV32IB-NEXT: bltz t2, .LBB13_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: sll a7, a0, t2
-; RV32IB-NEXT: j .LBB13_3
-; RV32IB-NEXT: .LBB13_2:
-; RV32IB-NEXT: sll a7, a1, a4
-; RV32IB-NEXT: sub a5, a6, a5
+; RV32IB-NEXT: sub t0, a6, a5
; RV32IB-NEXT: srli a1, a0, 1
-; RV32IB-NEXT: srl a1, a1, a5
+; RV32IB-NEXT: srl a1, a1, t0
; RV32IB-NEXT: or a7, a7, a1
-; RV32IB-NEXT: .LBB13_3:
-; RV32IB-NEXT: not t1, a4
+; RV32IB-NEXT: addi t1, a5, -32
+; RV32IB-NEXT: sll t0, a0, t1
+; RV32IB-NEXT: slti a1, t1, 0
+; RV32IB-NEXT: cmov t0, a1, a7, t0
+; RV32IB-NEXT: not a7, a4
+; RV32IB-NEXT: srli t4, a3, 1
+; RV32IB-NEXT: srl t2, t4, a7
; RV32IB-NEXT: addi a1, zero, 63
-; RV32IB-NEXT: andn a5, a1, a4
-; RV32IB-NEXT: addi a1, a5, -32
-; RV32IB-NEXT: srli t3, a3, 1
-; RV32IB-NEXT: bltz a1, .LBB13_7
-; RV32IB-NEXT: # %bb.4:
-; RV32IB-NEXT: mv t0, zero
-; RV32IB-NEXT: bgez a1, .LBB13_8
-; RV32IB-NEXT: .LBB13_5:
-; RV32IB-NEXT: fsri a1, a2, a3, 1
-; RV32IB-NEXT: srl a1, a1, t1
-; RV32IB-NEXT: sub a2, a6, a5
-; RV32IB-NEXT: slli a3, t3, 1
-; RV32IB-NEXT: sll a2, a3, a2
-; RV32IB-NEXT: or a2, a1, a2
-; RV32IB-NEXT: or a1, a7, t0
-; RV32IB-NEXT: bgez t2, .LBB13_9
-; RV32IB-NEXT: .LBB13_6:
+; RV32IB-NEXT: andn t3, a1, a4
+; RV32IB-NEXT: addi a5, t3, -32
+; RV32IB-NEXT: srai a1, a5, 31
+; RV32IB-NEXT: and a1, a1, t2
+; RV32IB-NEXT: or a1, t0, a1
+; RV32IB-NEXT: fsri a2, a2, a3, 1
+; RV32IB-NEXT: srl a7, a2, a7
+; RV32IB-NEXT: sub a3, a6, t3
+; RV32IB-NEXT: slli a2, t4, 1
+; RV32IB-NEXT: sll a2, a2, a3
+; RV32IB-NEXT: or a2, a7, a2
+; RV32IB-NEXT: srl a3, t4, a5
+; RV32IB-NEXT: slti a5, a5, 0
+; RV32IB-NEXT: cmov a2, a5, a2, a3
; RV32IB-NEXT: sll a0, a0, a4
+; RV32IB-NEXT: srai a3, t1, 31
+; RV32IB-NEXT: and a0, a3, a0
; RV32IB-NEXT: or a0, a0, a2
; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB13_7:
-; RV32IB-NEXT: srl t0, t3, t1
-; RV32IB-NEXT: bltz a1, .LBB13_5
-; RV32IB-NEXT: .LBB13_8:
-; RV32IB-NEXT: srl a2, t3, a1
-; RV32IB-NEXT: or a1, a7, t0
-; RV32IB-NEXT: bltz t2, .LBB13_6
-; RV32IB-NEXT: .LBB13_9:
-; RV32IB-NEXT: or a0, zero, a2
-; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: fshl_i64:
; RV32IBT: # %bb.0:
+; RV32IBT-NEXT: sll a7, a1, a4
; RV32IBT-NEXT: andi a5, a4, 63
-; RV32IBT-NEXT: addi t1, a5, -32
; RV32IBT-NEXT: addi a6, zero, 31
-; RV32IBT-NEXT: bltz t1, .LBB13_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: sll a7, a0, t1
-; RV32IBT-NEXT: j .LBB13_3
-; RV32IBT-NEXT: .LBB13_2:
-; RV32IBT-NEXT: sll a7, a1, a4
-; RV32IBT-NEXT: sub a5, a6, a5
+; RV32IBT-NEXT: sub t0, a6, a5
; RV32IBT-NEXT: srli a1, a0, 1
-; RV32IBT-NEXT: srl a1, a1, a5
+; RV32IBT-NEXT: srl a1, a1, t0
; RV32IBT-NEXT: or a7, a7, a1
-; RV32IBT-NEXT: .LBB13_3:
-; RV32IBT-NEXT: not a1, a4
-; RV32IBT-NEXT: andi t3, a1, 63
-; RV32IBT-NEXT: addi a5, t3, -32
-; RV32IBT-NEXT: srli t2, a3, 1
-; RV32IBT-NEXT: bltz a5, .LBB13_7
-; RV32IBT-NEXT: # %bb.4:
-; RV32IBT-NEXT: mv t0, zero
-; RV32IBT-NEXT: bgez a5, .LBB13_8
-; RV32IBT-NEXT: .LBB13_5:
+; RV32IBT-NEXT: addi t1, a5, -32
+; RV32IBT-NEXT: sll t0, a0, t1
+; RV32IBT-NEXT: slti a1, t1, 0
+; RV32IBT-NEXT: cmov t0, a1, a7, t0
+; RV32IBT-NEXT: not a5, a4
+; RV32IBT-NEXT: srli a7, a3, 1
+; RV32IBT-NEXT: srl t4, a7, a5
+; RV32IBT-NEXT: andi t2, a5, 63
+; RV32IBT-NEXT: addi t3, t2, -32
+; RV32IBT-NEXT: srai a1, t3, 31
+; RV32IBT-NEXT: and a1, a1, t4
+; RV32IBT-NEXT: or a1, t0, a1
; RV32IBT-NEXT: fsri a2, a2, a3, 1
-; RV32IBT-NEXT: srl a1, a2, a1
-; RV32IBT-NEXT: sub a2, a6, t3
-; RV32IBT-NEXT: slli a3, t2, 1
-; RV32IBT-NEXT: sll a2, a3, a2
-; RV32IBT-NEXT: or a2, a1, a2
-; RV32IBT-NEXT: or a1, a7, t0
-; RV32IBT-NEXT: bgez t1, .LBB13_9
-; RV32IBT-NEXT: .LBB13_6:
+; RV32IBT-NEXT: srl a2, a2, a5
+; RV32IBT-NEXT: sub a3, a6, t2
+; RV32IBT-NEXT: slli a5, a7, 1
+; RV32IBT-NEXT: sll a3, a5, a3
+; RV32IBT-NEXT: or a2, a2, a3
+; RV32IBT-NEXT: srl a3, a7, t3
+; RV32IBT-NEXT: slti a5, t3, 0
+; RV32IBT-NEXT: cmov a2, a5, a2, a3
; RV32IBT-NEXT: sll a0, a0, a4
+; RV32IBT-NEXT: srai a3, t1, 31
+; RV32IBT-NEXT: and a0, a3, a0
; RV32IBT-NEXT: or a0, a0, a2
-; RV32IBT-NEXT: ret
-; RV32IBT-NEXT: .LBB13_7:
-; RV32IBT-NEXT: srl t0, t2, a1
-; RV32IBT-NEXT: bltz a5, .LBB13_5
-; RV32IBT-NEXT: .LBB13_8:
-; RV32IBT-NEXT: srl a2, t2, a5
-; RV32IBT-NEXT: or a1, a7, t0
-; RV32IBT-NEXT: bltz t1, .LBB13_6
-; RV32IBT-NEXT: .LBB13_9:
-; RV32IBT-NEXT: or a0, zero, a2
; RV32IBT-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
ret i64 %1
@@ -745,101 +657,79 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
;
; RV32IB-LABEL: fshr_i64:
; RV32IB: # %bb.0:
+; RV32IB-NEXT: srl a7, a2, a4
; RV32IB-NEXT: andi a5, a4, 63
-; RV32IB-NEXT: addi t2, a5, -32
; RV32IB-NEXT: addi a6, zero, 31
-; RV32IB-NEXT: bltz t2, .LBB15_2
-; RV32IB-NEXT: # %bb.1:
-; RV32IB-NEXT: srl a7, a3, t2
-; RV32IB-NEXT: j .LBB15_3
-; RV32IB-NEXT: .LBB15_2:
-; RV32IB-NEXT: srl a7, a2, a4
-; RV32IB-NEXT: sub a5, a6, a5
+; RV32IB-NEXT: sub t0, a6, a5
; RV32IB-NEXT: slli a2, a3, 1
-; RV32IB-NEXT: sll a2, a2, a5
+; RV32IB-NEXT: sll a2, a2, t0
; RV32IB-NEXT: or a7, a7, a2
-; RV32IB-NEXT: .LBB15_3:
-; RV32IB-NEXT: not t1, a4
-; RV32IB-NEXT: addi a2, zero, 63
-; RV32IB-NEXT: andn a2, a2, a4
-; RV32IB-NEXT: addi a5, a2, -32
-; RV32IB-NEXT: slli t3, a0, 1
-; RV32IB-NEXT: bltz a5, .LBB15_7
-; RV32IB-NEXT: # %bb.4:
-; RV32IB-NEXT: mv t0, zero
-; RV32IB-NEXT: bgez a5, .LBB15_8
-; RV32IB-NEXT: .LBB15_5:
+; RV32IB-NEXT: addi t2, a5, -32
+; RV32IB-NEXT: srl t0, a3, t2
+; RV32IB-NEXT: slti a2, t2, 0
+; RV32IB-NEXT: cmov a7, a2, a7, t0
+; RV32IB-NEXT: not t3, a4
+; RV32IB-NEXT: slli t0, a0, 1
+; RV32IB-NEXT: sll t1, t0, t3
+; RV32IB-NEXT: addi a5, zero, 63
+; RV32IB-NEXT: andn t4, a5, a4
+; RV32IB-NEXT: addi a2, t4, -32
+; RV32IB-NEXT: srai a5, a2, 31
+; RV32IB-NEXT: and a5, a5, t1
+; RV32IB-NEXT: or a7, a5, a7
; RV32IB-NEXT: fsri a1, a0, a1, 31
-; RV32IB-NEXT: sll a1, a1, t1
-; RV32IB-NEXT: sub a2, a6, a2
+; RV32IB-NEXT: sll a1, a1, t3
+; RV32IB-NEXT: sub a5, a6, t4
; RV32IB-NEXT: sbclri a0, a0, 31
-; RV32IB-NEXT: srl a0, a0, a2
-; RV32IB-NEXT: or a1, a1, a0
-; RV32IB-NEXT: or a0, t0, a7
-; RV32IB-NEXT: bgez t2, .LBB15_9
-; RV32IB-NEXT: .LBB15_6:
-; RV32IB-NEXT: srl a2, a3, a4
-; RV32IB-NEXT: or a1, a1, a2
-; RV32IB-NEXT: ret
-; RV32IB-NEXT: .LBB15_7:
-; RV32IB-NEXT: sll t0, t3, t1
-; RV32IB-NEXT: bltz a5, .LBB15_5
-; RV32IB-NEXT: .LBB15_8:
-; RV32IB-NEXT: sll a1, t3, a5
-; RV32IB-NEXT: or a0, t0, a7
-; RV32IB-NEXT: bltz t2, .LBB15_6
-; RV32IB-NEXT: .LBB15_9:
-; RV32IB-NEXT: or a1, a1, zero
+; RV32IB-NEXT: srl a0, a0, a5
+; RV32IB-NEXT: or a0, a1, a0
+; RV32IB-NEXT: sll a1, t0, a2
+; RV32IB-NEXT: slti a2, a2, 0
+; RV32IB-NEXT: cmov a0, a2, a0, a1
+; RV32IB-NEXT: srl a1, a3, a4
+; RV32IB-NEXT: srai a2, t2, 31
+; RV32IB-NEXT: and a1, a2, a1
+; RV32IB-NEXT: or a1, a0, a1
+; RV32IB-NEXT: mv a0, a7
; RV32IB-NEXT: ret
;
; RV32IBT-LABEL: fshr_i64:
; RV32IBT: # %bb.0:
+; RV32IBT-NEXT: srl a7, a2, a4
; RV32IBT-NEXT: andi a5, a4, 63
-; RV32IBT-NEXT: addi t1, a5, -32
; RV32IBT-NEXT: addi a6, zero, 31
-; RV32IBT-NEXT: bltz t1, .LBB15_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: srl a7, a3, t1
-; RV32IBT-NEXT: j .LBB15_3
-; RV32IBT-NEXT: .LBB15_2:
-; RV32IBT-NEXT: srl a7, a2, a4
-; RV32IBT-NEXT: sub a5, a6, a5
+; RV32IBT-NEXT: sub t0, a6, a5
; RV32IBT-NEXT: slli a2, a3, 1
-; RV32IBT-NEXT: sll a2, a2, a5
+; RV32IBT-NEXT: sll a2, a2, t0
; RV32IBT-NEXT: or a7, a7, a2
-; RV32IBT-NEXT: .LBB15_3:
-; RV32IBT-NEXT: not a2, a4
-; RV32IBT-NEXT: andi t2, a2, 63
-; RV32IBT-NEXT: addi a5, t2, -32
-; RV32IBT-NEXT: slli t3, a0, 1
-; RV32IBT-NEXT: bltz a5, .LBB15_7
-; RV32IBT-NEXT: # %bb.4:
-; RV32IBT-NEXT: mv t0, zero
-; RV32IBT-NEXT: bgez a5, .LBB15_8
-; RV32IBT-NEXT: .LBB15_5:
-; RV32IBT-NEXT: lui a5, 524288
-; RV32IBT-NEXT: addi a5, a5, -1
-; RV32IBT-NEXT: and t3, a0, a5
-; RV32IBT-NEXT: sub a5, a6, t2
-; RV32IBT-NEXT: srl a5, t3, a5
+; RV32IBT-NEXT: addi t2, a5, -32
+; RV32IBT-NEXT: srl t0, a3, t2
+; RV32IBT-NEXT: slti a2, t2, 0
+; RV32IBT-NEXT: cmov a7, a2, a7, t0
+; RV32IBT-NEXT: not t4, a4
+; RV32IBT-NEXT: slli t0, a0, 1
+; RV32IBT-NEXT: sll t1, t0, t4
+; RV32IBT-NEXT: andi t3, t4, 63
+; RV32IBT-NEXT: addi a5, t3, -32
+; RV32IBT-NEXT: srai a2, a5, 31
+; RV32IBT-NEXT: and a2, a2, t1
+; RV32IBT-NEXT: or a7, a2, a7
+; RV32IBT-NEXT: lui a2, 524288
+; RV32IBT-NEXT: addi a2, a2, -1
+; RV32IBT-NEXT: and t1, a0, a2
+; RV32IBT-NEXT: sub a2, a6, t3
+; RV32IBT-NEXT: srl a2, t1, a2
; RV32IBT-NEXT: fsri a0, a0, a1, 31
-; RV32IBT-NEXT: sll a0, a0, a2
-; RV32IBT-NEXT: or a1, a0, a5
-; RV32IBT-NEXT: or a0, t0, a7
-; RV32IBT-NEXT: bgez t1, .LBB15_9
-; RV32IBT-NEXT: .LBB15_6:
-; RV32IBT-NEXT: srl a2, a3, a4
-; RV32IBT-NEXT: or a1, a1, a2
-; RV32IBT-NEXT: ret
-; RV32IBT-NEXT: .LBB15_7:
-; RV32IBT-NEXT: sll t0, t3, a2
-; RV32IBT-NEXT: bltz a5, .LBB15_5
-; RV32IBT-NEXT: .LBB15_8:
-; RV32IBT-NEXT: sll a1, t3, a5
-; RV32IBT-NEXT: or a0, t0, a7
-; RV32IBT-NEXT: bltz t1, .LBB15_6
-; RV32IBT-NEXT: .LBB15_9:
-; RV32IBT-NEXT: or a1, a1, zero
+; RV32IBT-NEXT: sll a0, a0, t4
+; RV32IBT-NEXT: or a0, a0, a2
+; RV32IBT-NEXT: sll a1, t0, a5
+; RV32IBT-NEXT: slti a2, a5, 0
+; RV32IBT-NEXT: cmov a0, a2, a0, a1
+; RV32IBT-NEXT: srl a1, a3, a4
+; RV32IBT-NEXT: srai a2, t2, 31
+; RV32IBT-NEXT: and a1, a2, a1
+; RV32IBT-NEXT: or a1, a0, a1
+; RV32IBT-NEXT: mv a0, a7
; RV32IBT-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbt.ll b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
index 72c3f2d45a33..61ebe6947c42 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
@@ -91,18 +91,14 @@ define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c,
;
; RV64IB-LABEL: cmov_sle_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bge a2, a1, .LBB3_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB3_2:
+; RV64IB-NEXT: slt a1, a2, a1
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_sle_i32:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bge a2, a1, .LBB3_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB3_2:
+; RV64IBT-NEXT: slt a1, a2, a1
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -120,18 +116,14 @@ define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c,
;
; RV64IB-LABEL: cmov_sge_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bge a1, a2, .LBB4_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB4_2:
+; RV64IB-NEXT: slt a1, a1, a2
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_sge_i32:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bge a1, a2, .LBB4_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB4_2:
+; RV64IBT-NEXT: slt a1, a1, a2
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -149,18 +141,14 @@ define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c,
;
; RV64IB-LABEL: cmov_ule_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bgeu a2, a1, .LBB5_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB5_2:
+; RV64IB-NEXT: sltu a1, a2, a1
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_ule_i32:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bgeu a2, a1, .LBB5_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB5_2:
+; RV64IBT-NEXT: sltu a1, a2, a1
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -178,18 +166,14 @@ define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c,
;
; RV64IB-LABEL: cmov_uge_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bgeu a1, a2, .LBB6_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB6_2:
+; RV64IB-NEXT: sltu a1, a1, a2
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_uge_i32:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bgeu a1, a2, .LBB6_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB6_2:
+; RV64IBT-NEXT: sltu a1, a1, a2
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
@@ -231,18 +215,14 @@ define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV64IB-LABEL: cmov_sle_i64:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bge a2, a1, .LBB8_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB8_2:
+; RV64IB-NEXT: slt a1, a2, a1
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_sle_i64:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bge a2, a1, .LBB8_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB8_2:
+; RV64IBT-NEXT: slt a1, a2, a1
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -260,18 +240,14 @@ define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV64IB-LABEL: cmov_sge_i64:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bge a1, a2, .LBB9_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB9_2:
+; RV64IB-NEXT: slt a1, a1, a2
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_sge_i64:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bge a1, a2, .LBB9_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB9_2:
+; RV64IBT-NEXT: slt a1, a1, a2
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -289,18 +265,14 @@ define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV64IB-LABEL: cmov_ule_i64:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bgeu a2, a1, .LBB10_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB10_2:
+; RV64IB-NEXT: sltu a1, a2, a1
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_ule_i64:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bgeu a2, a1, .LBB10_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB10_2:
+; RV64IBT-NEXT: sltu a1, a2, a1
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
@@ -318,18 +290,14 @@ define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
;
; RV64IB-LABEL: cmov_uge_i64:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: bgeu a1, a2, .LBB11_2
-; RV64IB-NEXT: # %bb.1:
-; RV64IB-NEXT: mv a0, a3
-; RV64IB-NEXT: .LBB11_2:
+; RV64IB-NEXT: sltu a1, a1, a2
+; RV64IB-NEXT: cmov a0, a1, a3, a0
; RV64IB-NEXT: ret
;
; RV64IBT-LABEL: cmov_uge_i64:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: bgeu a1, a2, .LBB11_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB11_2:
+; RV64IBT-NEXT: sltu a1, a1, a2
+; RV64IBT-NEXT: cmov a0, a1, a3, a0
; RV64IBT-NEXT: ret
%tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll
index 61ba35b69dfa..28237de126be 100644
--- a/llvm/test/CodeGen/RISCV/select-and.ll
+++ b/llvm/test/CodeGen/RISCV/select-and.ll
@@ -24,12 +24,8 @@ define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c,
;
; RV32IBT-LABEL: select_of_and:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: and a1, a0, a1
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: bnez a1, .LBB0_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB0_2:
+; RV32IBT-NEXT: and a0, a0, a1
+; RV32IBT-NEXT: cmov a0, a0, a2, a3
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_of_and:
@@ -44,12 +40,8 @@ define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c,
;
; RV64IBT-LABEL: select_of_and:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: and a1, a0, a1
-; RV64IBT-NEXT: mv a0, a2
-; RV64IBT-NEXT: bnez a1, .LBB0_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB0_2:
+; RV64IBT-NEXT: and a0, a0, a1
+; RV64IBT-NEXT: cmov a0, a0, a2, a3
; RV64IBT-NEXT: ret
%1 = and i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d
diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll
index f3feb68b2052..b24e1d775ffb 100644
--- a/llvm/test/CodeGen/RISCV/select-bare.ll
+++ b/llvm/test/CodeGen/RISCV/select-bare.ll
@@ -17,12 +17,8 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
;
; RV32IBT-LABEL: bare_select:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: andi a3, a0, 1
-; RV32IBT-NEXT: mv a0, a1
-; RV32IBT-NEXT: bnez a3, .LBB0_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_2:
+; RV32IBT-NEXT: andi a0, a0, 1
+; RV32IBT-NEXT: cmov a0, a0, a1, a2
; RV32IBT-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
@@ -41,12 +37,8 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
;
; RV32IBT-LABEL: bare_select_float:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: andi a3, a0, 1
-; RV32IBT-NEXT: mv a0, a1
-; RV32IBT-NEXT: bnez a3, .LBB1_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB1_2:
+; RV32IBT-NEXT: andi a0, a0, 1
+; RV32IBT-NEXT: cmov a0, a0, a1, a2
; RV32IBT-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 405c88a5277f..e9d865b73c2d 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -62,55 +62,35 @@ define i32 @foo(i32 %a, i32 *%b) nounwind {
; RV32IBT-LABEL: foo:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: beq a0, a2, .LBB0_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_2:
+; RV32IBT-NEXT: lw a3, 0(a1)
+; RV32IBT-NEXT: xor a4, a0, a2
+; RV32IBT-NEXT: cmov a0, a4, a2, a0
; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bne a0, a2, .LBB0_4
-; RV32IBT-NEXT: # %bb.3:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_4:
+; RV32IBT-NEXT: xor a4, a0, a3
+; RV32IBT-NEXT: cmov a0, a4, a0, a3
+; RV32IBT-NEXT: lw a3, 0(a1)
+; RV32IBT-NEXT: sltu a4, a2, a0
+; RV32IBT-NEXT: cmov a0, a4, a0, a2
; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bltu a2, a0, .LBB0_6
-; RV32IBT-NEXT: # %bb.5:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_6:
+; RV32IBT-NEXT: sltu a4, a0, a3
+; RV32IBT-NEXT: cmov a0, a4, a3, a0
+; RV32IBT-NEXT: lw a3, 0(a1)
+; RV32IBT-NEXT: sltu a4, a0, a2
+; RV32IBT-NEXT: cmov a0, a4, a0, a2
; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bgeu a0, a2, .LBB0_8
-; RV32IBT-NEXT: # %bb.7:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_8:
+; RV32IBT-NEXT: sltu a4, a3, a0
+; RV32IBT-NEXT: cmov a0, a4, a3, a0
+; RV32IBT-NEXT: lw a3, 0(a1)
+; RV32IBT-NEXT: slt a4, a2, a0
+; RV32IBT-NEXT: cmov a0, a4, a0, a2
; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bltu a0, a2, .LBB0_10
-; RV32IBT-NEXT: # %bb.9:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_10:
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bgeu a2, a0, .LBB0_12
-; RV32IBT-NEXT: # %bb.11:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_12:
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: blt a2, a0, .LBB0_14
-; RV32IBT-NEXT: # %bb.13:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_14:
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: bge a0, a2, .LBB0_16
-; RV32IBT-NEXT: # %bb.15:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_16:
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: blt a0, a2, .LBB0_18
-; RV32IBT-NEXT: # %bb.17:
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: .LBB0_18:
+; RV32IBT-NEXT: slt a4, a0, a3
; RV32IBT-NEXT: lw a1, 0(a1)
-; RV32IBT-NEXT: bge a1, a0, .LBB0_20
-; RV32IBT-NEXT: # %bb.19:
-; RV32IBT-NEXT: mv a0, a1
-; RV32IBT-NEXT: .LBB0_20:
+; RV32IBT-NEXT: cmov a0, a4, a3, a0
+; RV32IBT-NEXT: slt a3, a0, a2
+; RV32IBT-NEXT: cmov a0, a3, a0, a2
+; RV32IBT-NEXT: slt a2, a1, a0
+; RV32IBT-NEXT: cmov a0, a2, a1, a0
; RV32IBT-NEXT: ret
%val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %a, %val1
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 7c9b42f4f4ea..c98c3d13c09f 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -179,22 +179,16 @@ define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
;
; RV32IBT-LABEL: select_const_int_harder:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: mv a1, a0
-; RV32IBT-NEXT: addi a0, zero, 6
-; RV32IBT-NEXT: bnez a1, .LBB3_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: addi a0, zero, 38
-; RV32IBT-NEXT: .LBB3_2:
+; RV32IBT-NEXT: addi a1, zero, 38
+; RV32IBT-NEXT: addi a2, zero, 6
+; RV32IBT-NEXT: cmov a0, a0, a2, a1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_int_harder:
; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: mv a1, a0
-; RV32IFBT-NEXT: addi a0, zero, 6
-; RV32IFBT-NEXT: bnez a1, .LBB3_2
-; RV32IFBT-NEXT: # %bb.1:
-; RV32IFBT-NEXT: addi a0, zero, 38
-; RV32IFBT-NEXT: .LBB3_2:
+; RV32IFBT-NEXT: addi a1, zero, 38
+; RV32IFBT-NEXT: addi a2, zero, 6
+; RV32IFBT-NEXT: cmov a0, a0, a2, a1
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_int_harder:
@@ -219,22 +213,16 @@ define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
;
; RV64IBT-LABEL: select_const_int_harder:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: mv a1, a0
-; RV64IBT-NEXT: addi a0, zero, 6
-; RV64IBT-NEXT: bnez a1, .LBB3_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: addi a0, zero, 38
-; RV64IBT-NEXT: .LBB3_2:
+; RV64IBT-NEXT: addi a1, zero, 38
+; RV64IBT-NEXT: addi a2, zero, 6
+; RV64IBT-NEXT: cmov a0, a0, a2, a1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_int_harder:
; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: mv a1, a0
-; RV64IFDBT-NEXT: addi a0, zero, 6
-; RV64IFDBT-NEXT: bnez a1, .LBB3_2
-; RV64IFDBT-NEXT: # %bb.1:
-; RV64IFDBT-NEXT: addi a0, zero, 38
-; RV64IFDBT-NEXT: .LBB3_2:
+; RV64IFDBT-NEXT: addi a1, zero, 38
+; RV64IFDBT-NEXT: addi a2, zero, 6
+; RV64IFDBT-NEXT: cmov a0, a0, a2, a1
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, i32 6, i32 38
ret i32 %1
@@ -267,12 +255,9 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
;
; RV32IBT-LABEL: select_const_fp:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: mv a1, a0
-; RV32IBT-NEXT: lui a0, 263168
-; RV32IBT-NEXT: bnez a1, .LBB4_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: lui a0, 264192
-; RV32IBT-NEXT: .LBB4_2:
+; RV32IBT-NEXT: lui a1, 264192
+; RV32IBT-NEXT: lui a2, 263168
+; RV32IBT-NEXT: cmov a0, a0, a2, a1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_fp:
@@ -315,12 +300,9 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
;
; RV64IBT-LABEL: select_const_fp:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: mv a1, a0
-; RV64IBT-NEXT: lui a0, 263168
-; RV64IBT-NEXT: bnez a1, .LBB4_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: lui a0, 264192
-; RV64IBT-NEXT: .LBB4_2:
+; RV64IBT-NEXT: lui a1, 264192
+; RV64IBT-NEXT: lui a2, 263168
+; RV64IBT-NEXT: cmov a0, a0, a2, a1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_fp:
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index 35c1dd5e50fc..b6ecf3930b24 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -28,13 +28,9 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
; RV32IBT-LABEL: cmovcc64:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a5, zero, 123
-; RV32IBT-NEXT: beq a0, a5, .LBB0_2
-; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: mv a1, a3
-; RV32IBT-NEXT: mv a2, a4
-; RV32IBT-NEXT: .LBB0_2: # %entry
-; RV32IBT-NEXT: mv a0, a1
-; RV32IBT-NEXT: mv a1, a2
+; RV32IBT-NEXT: xor a5, a0, a5
+; RV32IBT-NEXT: cmov a0, a5, a3, a1
+; RV32IBT-NEXT: cmov a1, a5, a4, a2
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovcc64:
@@ -50,11 +46,8 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
; RV64IBT-LABEL: cmovcc64:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a3, zero, 123
-; RV64IBT-NEXT: beq a0, a3, .LBB0_2
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: mv a1, a2
-; RV64IBT-NEXT: .LBB0_2: # %entry
-; RV64IBT-NEXT: mv a0, a1
+; RV64IBT-NEXT: xor a0, a0, a3
+; RV64IBT-NEXT: cmov a0, a0, a2, a1
; RV64IBT-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 123
@@ -141,13 +134,9 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV64IBT-LABEL: cmovcc128:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a5, zero, 123
-; RV64IBT-NEXT: beq a0, a5, .LBB1_2
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: mv a1, a3
-; RV64IBT-NEXT: mv a2, a4
-; RV64IBT-NEXT: .LBB1_2: # %entry
-; RV64IBT-NEXT: mv a0, a1
-; RV64IBT-NEXT: mv a1, a2
+; RV64IBT-NEXT: xor a5, a0, a5
+; RV64IBT-NEXT: cmov a0, a5, a3, a1
+; RV64IBT-NEXT: cmov a1, a5, a4, a2
; RV64IBT-NEXT: ret
entry:
%cmp = icmp eq i64 %a, 123
@@ -171,13 +160,8 @@ define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
; RV32IBT-LABEL: cmov64:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a5, a0, 1
-; RV32IBT-NEXT: mv a0, a1
-; RV32IBT-NEXT: bnez a5, .LBB2_2
-; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: mv a2, a4
-; RV32IBT-NEXT: .LBB2_2: # %entry
-; RV32IBT-NEXT: mv a1, a2
+; RV32IBT-NEXT: cmov a0, a5, a1, a3
+; RV32IBT-NEXT: cmov a1, a5, a2, a4
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmov64:
@@ -192,12 +176,8 @@ define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
;
; RV64IBT-LABEL: cmov64:
; RV64IBT: # %bb.0: # %entry
-; RV64IBT-NEXT: andi a3, a0, 1
-; RV64IBT-NEXT: mv a0, a1
-; RV64IBT-NEXT: bnez a3, .LBB2_2
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: mv a0, a2
-; RV64IBT-NEXT: .LBB2_2: # %entry
+; RV64IBT-NEXT: andi a0, a0, 1
+; RV64IBT-NEXT: cmov a0, a0, a1, a2
; RV64IBT-NEXT: ret
entry:
%cond = select i1 %a, i64 %b, i64 %c
@@ -245,40 +225,25 @@ define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
;
; RV32IBT-LABEL: cmov128:
; RV32IBT: # %bb.0: # %entry
+; RV32IBT-NEXT: addi a6, a3, 12
+; RV32IBT-NEXT: addi a7, a2, 12
+; RV32IBT-NEXT: addi t0, a3, 8
+; RV32IBT-NEXT: addi t1, a2, 8
+; RV32IBT-NEXT: addi a4, a3, 4
+; RV32IBT-NEXT: addi a5, a2, 4
; RV32IBT-NEXT: andi a1, a1, 1
-; RV32IBT-NEXT: mv a4, a2
-; RV32IBT-NEXT: bnez a1, .LBB3_2
-; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: mv a4, a3
-; RV32IBT-NEXT: .LBB3_2: # %entry
-; RV32IBT-NEXT: bnez a1, .LBB3_5
-; RV32IBT-NEXT: # %bb.3: # %entry
-; RV32IBT-NEXT: addi a7, a3, 4
-; RV32IBT-NEXT: beqz a1, .LBB3_6
-; RV32IBT-NEXT: .LBB3_4:
-; RV32IBT-NEXT: addi a5, a2, 8
-; RV32IBT-NEXT: j .LBB3_7
-; RV32IBT-NEXT: .LBB3_5:
-; RV32IBT-NEXT: addi a7, a2, 4
-; RV32IBT-NEXT: bnez a1, .LBB3_4
-; RV32IBT-NEXT: .LBB3_6: # %entry
-; RV32IBT-NEXT: addi a5, a3, 8
-; RV32IBT-NEXT: .LBB3_7: # %entry
-; RV32IBT-NEXT: lw a6, 0(a4)
-; RV32IBT-NEXT: lw a7, 0(a7)
-; RV32IBT-NEXT: lw a4, 0(a5)
-; RV32IBT-NEXT: bnez a1, .LBB3_9
-; RV32IBT-NEXT: # %bb.8: # %entry
-; RV32IBT-NEXT: addi a1, a3, 12
-; RV32IBT-NEXT: j .LBB3_10
-; RV32IBT-NEXT: .LBB3_9:
-; RV32IBT-NEXT: addi a1, a2, 12
-; RV32IBT-NEXT: .LBB3_10: # %entry
+; RV32IBT-NEXT: cmov a2, a1, a2, a3
+; RV32IBT-NEXT: cmov a3, a1, a5, a4
+; RV32IBT-NEXT: cmov a4, a1, t1, t0
+; RV32IBT-NEXT: cmov a1, a1, a7, a6
; RV32IBT-NEXT: lw a1, 0(a1)
+; RV32IBT-NEXT: lw a4, 0(a4)
+; RV32IBT-NEXT: lw a3, 0(a3)
+; RV32IBT-NEXT: lw a2, 0(a2)
; RV32IBT-NEXT: sw a1, 12(a0)
; RV32IBT-NEXT: sw a4, 8(a0)
-; RV32IBT-NEXT: sw a7, 4(a0)
-; RV32IBT-NEXT: sw a6, 0(a0)
+; RV32IBT-NEXT: sw a3, 4(a0)
+; RV32IBT-NEXT: sw a2, 0(a0)
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmov128:
@@ -296,13 +261,8 @@ define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV64IBT-LABEL: cmov128:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a5, a0, 1
-; RV64IBT-NEXT: mv a0, a1
-; RV64IBT-NEXT: bnez a5, .LBB3_2
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: mv a2, a4
-; RV64IBT-NEXT: .LBB3_2: # %entry
-; RV64IBT-NEXT: mv a1, a2
+; RV64IBT-NEXT: cmov a0, a5, a1, a3
+; RV64IBT-NEXT: cmov a1, a5, a2, a4
; RV64IBT-NEXT: ret
entry:
%cond = select i1 %a, i128 %b, i128 %c
@@ -475,20 +435,10 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32IBT-LABEL: cmovccdep:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a4, zero, 123
-; RV32IBT-NEXT: bne a0, a4, .LBB6_3
-; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: mv a2, a1
-; RV32IBT-NEXT: bne a0, a4, .LBB6_4
-; RV32IBT-NEXT: .LBB6_2: # %entry
-; RV32IBT-NEXT: add a0, a1, a2
-; RV32IBT-NEXT: ret
-; RV32IBT-NEXT: .LBB6_3: # %entry
-; RV32IBT-NEXT: mv a1, a2
-; RV32IBT-NEXT: mv a2, a1
-; RV32IBT-NEXT: beq a0, a4, .LBB6_2
-; RV32IBT-NEXT: .LBB6_4: # %entry
-; RV32IBT-NEXT: mv a2, a3
-; RV32IBT-NEXT: add a0, a1, a2
+; RV32IBT-NEXT: xor a0, a0, a4
+; RV32IBT-NEXT: cmov a1, a0, a2, a1
+; RV32IBT-NEXT: cmov a0, a0, a3, a1
+; RV32IBT-NEXT: add a0, a1, a0
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovccdep:
@@ -513,20 +463,10 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV64IBT-LABEL: cmovccdep:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a4, zero, 123
-; RV64IBT-NEXT: bne a0, a4, .LBB6_3
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: mv a2, a1
-; RV64IBT-NEXT: bne a0, a4, .LBB6_4
-; RV64IBT-NEXT: .LBB6_2: # %entry
-; RV64IBT-NEXT: addw a0, a1, a2
-; RV64IBT-NEXT: ret
-; RV64IBT-NEXT: .LBB6_3: # %entry
-; RV64IBT-NEXT: mv a1, a2
-; RV64IBT-NEXT: mv a2, a1
-; RV64IBT-NEXT: beq a0, a4, .LBB6_2
-; RV64IBT-NEXT: .LBB6_4: # %entry
-; RV64IBT-NEXT: mv a2, a3
-; RV64IBT-NEXT: addw a0, a1, a2
+; RV64IBT-NEXT: xor a0, a0, a4
+; RV64IBT-NEXT: cmov a1, a0, a2, a1
+; RV64IBT-NEXT: cmov a0, a0, a3, a1
+; RV64IBT-NEXT: addw a0, a1, a0
; RV64IBT-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 123
@@ -559,20 +499,11 @@ define i32 @cmov
diff cc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
;
; RV32IBT-LABEL: cmov
diff cc:
; RV32IBT: # %bb.0: # %entry
-; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: andi a1, a1, 1
-; RV32IBT-NEXT: beqz a0, .LBB7_3
-; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: beqz a1, .LBB7_4
-; RV32IBT-NEXT: .LBB7_2: # %entry
-; RV32IBT-NEXT: add a0, a2, a4
-; RV32IBT-NEXT: ret
-; RV32IBT-NEXT: .LBB7_3: # %entry
-; RV32IBT-NEXT: mv a2, a3
-; RV32IBT-NEXT: bnez a1, .LBB7_2
-; RV32IBT-NEXT: .LBB7_4: # %entry
-; RV32IBT-NEXT: mv a4, a5
-; RV32IBT-NEXT: add a0, a2, a4
+; RV32IBT-NEXT: andi a0, a0, 1
+; RV32IBT-NEXT: cmov a0, a0, a2, a3
+; RV32IBT-NEXT: cmov a1, a1, a4, a5
+; RV32IBT-NEXT: add a0, a0, a1
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmov
diff cc:
@@ -595,20 +526,11 @@ define i32 @cmov
diff cc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
;
; RV64IBT-LABEL: cmov
diff cc:
; RV64IBT: # %bb.0: # %entry
-; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: andi a1, a1, 1
-; RV64IBT-NEXT: beqz a0, .LBB7_3
-; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: beqz a1, .LBB7_4
-; RV64IBT-NEXT: .LBB7_2: # %entry
-; RV64IBT-NEXT: addw a0, a2, a4
-; RV64IBT-NEXT: ret
-; RV64IBT-NEXT: .LBB7_3: # %entry
-; RV64IBT-NEXT: mv a2, a3
-; RV64IBT-NEXT: bnez a1, .LBB7_2
-; RV64IBT-NEXT: .LBB7_4: # %entry
-; RV64IBT-NEXT: mv a4, a5
-; RV64IBT-NEXT: addw a0, a2, a4
+; RV64IBT-NEXT: andi a0, a0, 1
+; RV64IBT-NEXT: cmov a0, a0, a2, a3
+; RV64IBT-NEXT: cmov a1, a1, a4, a5
+; RV64IBT-NEXT: addw a0, a0, a1
; RV64IBT-NEXT: ret
entry:
%cond1 = select i1 %a, i32 %c, i32 %d
diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll
index 1bcfad0378de..3c09943eb6f9 100644
--- a/llvm/test/CodeGen/RISCV/select-or.ll
+++ b/llvm/test/CodeGen/RISCV/select-or.ll
@@ -24,12 +24,8 @@ define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i
;
; RV32IBT-LABEL: select_of_or:
; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: or a1, a0, a1
-; RV32IBT-NEXT: mv a0, a2
-; RV32IBT-NEXT: bnez a1, .LBB0_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, a3
-; RV32IBT-NEXT: .LBB0_2:
+; RV32IBT-NEXT: or a0, a0, a1
+; RV32IBT-NEXT: cmov a0, a0, a2, a3
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_of_or:
@@ -44,12 +40,8 @@ define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i
;
; RV64IBT-LABEL: select_of_or:
; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: or a1, a0, a1
-; RV64IBT-NEXT: mv a0, a2
-; RV64IBT-NEXT: bnez a1, .LBB0_2
-; RV64IBT-NEXT: # %bb.1:
-; RV64IBT-NEXT: mv a0, a3
-; RV64IBT-NEXT: .LBB0_2:
+; RV64IBT-NEXT: or a0, a0, a1
+; RV64IBT-NEXT: cmov a0, a0, a2, a3
; RV64IBT-NEXT: ret
%1 = or i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d
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