[PATCH] D94931: [RISCV] Add attribute support for all supported extensions

[Simon Cook via Phabricator via llvm-commits]

simoncook added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/attributes.ll:63
+; RV32ZVAMO: .attribute 5, "rv32i2p0_v0p9_zvamo0p9"
+; RV32ZVLSSEG: .attribute 5, "rv32i2p0_v0p9_zvlsseg0p9"
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
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kito-cheng wrote:
> `rv32i2p0_zvlsseg0p9` rather than `rv32i2p0_zvlsseg0p9` here, it's kind of weird, but in theory `zvlsseg` is not implied `v`.
> 
> `zvamo` is same situation too.
Ok thanks for clarifying this. Looking at `RISCV.td` it looks like the implications is the wrong way around `zvamo` implies `v` but not the other way around. I'll switch this the other way round for the update on this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94931/new/

https://reviews.llvm.org/D94931