[PATCH] D94480: [DAGCombine] Correct the result for sqrt even the iteration is zero

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sqrt-fastmath.ll:75-76
 ; CHECK-NEXT:    fmul v1.2s, v1.2s, v2.2s
-; CHECK-NEXT:    fcmeq v2.2s, v0.2s, #0.0
-; CHECK-NEXT:    bif v0.8b, v1.8b, v2.8b
+; CHECK-NEXT:    fcmeq v0.2s, v0.2s, #0.0
+; CHECK-NEXT:    bic v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    ret
----------------
The bif/bic difference seems logically fine and probably better overall since we're using less registers, but someone who knows AArch should comment. 

Also, it would be interesting to know why the code changed because we are seemingly producing the same set of SDNode ops? There might be another combine/lowering opportunity.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94480/new/

https://reviews.llvm.org/D94480