[PATCH] D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal.

[Hsiangkai Wang via Phabricator via llvm-commits]

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The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171

There are lots of test files need to be updated. It is too large to contain all of these test files in one commit to upload. I only add vadd test files to demonstrate the modification. If this patch is accepted, I will update all of these test files and commit them to the repository.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95134

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

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