[PATCH] D94615: [RISCV][WIP] Add RVV insertelt/extractelt scalable-vector patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1655
+    // Extract the lower XLEN bits of the correct vector element.
+    SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, Subtarget.getXLenVT(),
+                                Slidedown, Idx);
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@craig.topper is it acceptable to use `VMV_X_S` here, do you think? It relies on the instruction transferring the least-significant XLEN bits even if SEW is larger. However your comment of that node says that the result will never be less than the element size.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94615/new/

https://reviews.llvm.org/D94615