[PATCH] D95090: [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {

  uint_xlen_t rs1u = (uint32_t)rs1;
  return rs1u + rs2;

}

The 0.92 spec had the usages of rs1 and rs2 swapped.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95090

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64Zba.ll


Index: llvm/test/CodeGen/RISCV/rv64Zba.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64Zba.ll
+++ llvm/test/CodeGen/RISCV/rv64Zba.ll
@@ -40,12 +40,12 @@
 ;
 ; RV64IB-LABEL: adduw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a0, a1
+; RV64IB-NEXT:    add.uw a0, a1, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: adduw:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    add.uw a0, a0, a1
+; RV64IBA-NEXT:    add.uw a0, a1, a0
 ; RV64IBA-NEXT:    ret
   %and = and i64 %b, 4294967295
   %add = add i64 %and, %a
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -834,7 +834,7 @@
 let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
+def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
 }
 


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