[PATCH] D93708: [AMDGPU] Add a new Clamp Pattern to the GlobalISel Path.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp:146
+
+  Register MedDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+  MRI.setType(MedDst, S32);
----------------
Don't need the register classes. You can also hide the createRegister calls with the builder as well


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp:149
+
+  B.buildInstr(AMDGPU::V_MED3_I32,
+    {MedDst},
----------------
tsymalla wrote:
> arsenm wrote:
> > A pseudo here would also apply for the same reasons
> I will implement this as soon as I'll get access back to my machine. Is there a reason why in some cases pseudos exist, in some cases not?
If we need to change how the operation is selected based on the register banks, it definitely should use a regbankselectable pseudo with generic register operands. If there isn't a meaningful handling change depending on the register banks, there's less reason to use a pseudo.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93708/new/

https://reviews.llvm.org/D93708