[PATCH] D95074: [ARM] Fix STRT/STRHT/STRBT input/output operands

[Zhuojia Shen via Phabricator via llvm-commits]

chaosdefinition created this revision.
chaosdefinition added reviewers: t.p.northover, dmgreen, kristof.beyls, MeeraN, SjoerdMeijer, samparker.
Herald added subscribers: danielkiss, hiraditya.
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STRT, STRHT, and STRBT are store instructions and their source register $Rt should be treated as an input operand instead of an output operand.  This should fix things (e.g., liveness tracking in LivePhysRegs) if these instructions were used in CodeGen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95074

Files:
  llvm/lib/Target/ARM/ARMInstrThumb2.td


Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -1724,7 +1724,7 @@
 // only.
 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
-  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
+  : T2Ii8<(outs), (ins rGPR:$Rt, t2addrmode_imm8:$addr), ii, opc,
           "\t$Rt, $addr", []>, Sched<[WriteST]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;


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