[PATCH] D95036: [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets

[Daniil Fukalov via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
dfukalov marked an inline comment as done.
Closed by commit rG560d7e04113b: [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets (authored by dfukalov).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95036/new/

https://reviews.llvm.org/D95036

Files:
  llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
  llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
  llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
  llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
  llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
  llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
  llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
  llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
  llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
  llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
  llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/lib/Target/AMDGPU/GCNRegPressure.h
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
  llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
  llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp
  llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
  llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
  llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
  llvm/lib/Target/AMDGPU/R600FrameLowering.cpp
  llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
  llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
  llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
  llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
  llvm/lib/Target/AMDGPU/R600Packetizer.cpp
  llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
  llvm/lib/Target/AMDGPU/R600Subtarget.h
  llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
  llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
  llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  llvm/lib/Target/AMDGPU/SIModeRegister.cpp
  llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
  llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
  llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp

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