[PATCH] D95071: [AMDGPU] Fix the inconsistency in soffset for MUBUF stack accesses.

Christudasan Devadasan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 20 10:33:05 PST 2021


cdevadas created this revision.
cdevadas added reviewers: arsenm, scott.linder.
Herald added subscribers: kerbowa, arphaman, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
cdevadas requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

During instruction selection, there is an inconsistency in choosing
the initial soffset value. With certain early passes, this value is
getting modified and that brought additional fixup during
eliminateFrameIndex to work for all cases. This whole transformation
looks trivial and can be handled better.

This patch clearly defines the initial value for soffset and keeps it
unchanged before eliminateFrameIndex. The initial value must be zero
for MUBUF with a frame index. The non-frame index MUBUF forms that
use a raw offset from SP will have the stack register for soffset.
During frame elimination, the soffset remains zero for entry functions
with zero dynamic allocas and no callsites, or else is updated to the
appropriate frame/stack register.

Also, did some code clean up and made all asserts around soffset
stricter to match.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95071

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
  llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
  llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
  llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

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