[PATCH] D95044: IR+AArch64: add `swiftasync` function parameter attribute

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: dexonsmith, pzheng, jdoerfert, danielkiss, pengfei, steven_wu, hiraditya, kristof.beyls, mcrosier.
t.p.northover requested review of this revision.
Herald added a project: LLVM.

Swift is getting some new asynchronous execution abilities which means functions will want to pass special execution contexts along in a way that is preserved by unaware functions much like `swiftself`. So this adds a parallel attribute to support that, which will map to a callee saved-register. That accounts for the fairly straightforward IR changes here.

Also, when this kind of argument is present, much of the control flow will be via guaranteed tail-calls which since they destroy the stack frame don't preserve backtrace information well. So when one of these contexts is present it will extend the usual (on AArch64) `[FP, LR]` frame record by putting the context just before it: `[Ctx, FP, LR]` (before rather than afterwards so that the same layout can be used on x86 where `callq` pushes the return address).

Finally, so that system tools and other things capturing stack traces can detect this kind of frame, the in-memory `FP` gets bit 60 set to 1.

On arm64e, this context will be signed in an address-discriminated way.


https://reviews.llvm.org/D95044

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/CodeGen/TargetCallingConv.h
  llvm/include/llvm/CodeGen/TargetFrameLowering.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/include/llvm/IR/Attributes.td
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Target/TargetCallingConv.td
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/AsmParser/LLToken.h
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/IR/Attributes.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Target/AArch64/AArch64CallingConvention.td
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64FastISel.cpp
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/lib/Target/AArch64/AArch64FrameLowering.h
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
  llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
  llvm/lib/Transforms/Utils/CodeExtractor.cpp
  llvm/test/CodeGen/AArch64/swift-async-reg.ll
  llvm/test/CodeGen/AArch64/swift-async-unwind.ll
  llvm/test/CodeGen/AArch64/swift-async.ll

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