[PATCH] D93614: [RISCV] New vector load/store in V extension v1.0

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 317841.
HsiangKai added a comment.

Delete redundant test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93614/new/

https://reviews.llvm.org/D93614

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll
  llvm/test/MC/RISCV/rvv/aliases.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s