[PATCH] D95028: [RISCV] Add intrinsics for vector unordered indexed loads in RVV 1.0

[ShihPo Hung via Phabricator via llvm-commits]

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1. Add unordered indexed load: vluxei
2. Rename existing indexed load/store intrinsics:

vloxe -> vloxei
vsuxe -> vsuxei
vsoxe -> vsoxei


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95028

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll