[PATCH] D93612: [RISCV] Update V instructions constraints to conform to v1.0

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 317777.
HsiangKai added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93612/new/

https://reviews.llvm.org/D93612

Files:
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/sub.s

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