[PATCH] D94730: [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGce8b3937ddad: [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D94730?vs=316799&id=317634#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94730/new/

https://reviews.llvm.org/D94730

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/select-and.ll
  llvm/test/CodeGen/RISCV/select-or.ll

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