[PATCH] D94763: [RISCV] Implement vlsseg intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:152
 
-void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned IntNo) {
+void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStride) {
   SDLoc DL(Node);
----------------
IsStride->IsStrided


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Comment at: llvm/test/CodeGen/RISCV/rvv/vlsseg.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
----------------
rv32?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94763/new/

https://reviews.llvm.org/D94763