[PATCH] D94974: [SLP] Try doubled MaxElts for stores vectorization

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 19 08:22:20 PST 2021


RKSimon added inline comments.


================
Comment at: llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll:174
 ; AVX256BW-NEXT:    store <4 x i64> [[TMP6]], <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 4) to <4 x i64>*), align 8
 ; AVX256BW-NEXT:    ret void
   %a0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 0), align 8
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please can you cleanup all these checks ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94974/new/

https://reviews.llvm.org/D94974



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