[PATCH] D94286: [RISCV] Add a VL output to vleff intrinsics.
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 19 06:14:42 PST 2021
HsiangKai added inline comments.
================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:110
+ [LLVMPointerType<LLVMMatchType<0>>, LLVMMatchType<1>],
+ [NoCapture<ArgIndex<0>>, IntrReadMem, IntrHasSideEffects]>,
+ RISCVVIntrinsic;
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Why do we need IntrHasSideEffects?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D94286/new/
https://reviews.llvm.org/D94286
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