[PATCH] D94960: [AMDGPU][MC] Add tfe disassembler support MIMG opcodes

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: dstuttard, foad, sebastian-ne.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
Petar.Avramovic requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
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With tfe on there can be a vgpr write to vdata+1.
Add tablegen support for 5 register vdata store.
This is required for 4 register vdata store with tfe.


https://reviews.llvm.org/D94960

Files:
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
  llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt

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