[PATCH] D94604: [CodeGen] Allow parallel uses of a resource

David Penry via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 18 11:28:35 PST 2021


dpenry added a comment.

In D94604#2504464 <https://reviews.llvm.org/D94604#2504464>, @andreadb wrote:

> I have only skimmed through this patch once, however I think that you can fix the problem in https://reviews.llvm.org/D94605 without introducing your new field `ResourceUses`.
>
> The "problematic" resource is M7UnitVPort
>
>   def M7UnitVPort  : ProcResource<2> { let BufferSize = 0; }
>
> In your case, you want to allow the consumption of both resource units from a single write.
> You can do that if you convert M7UnitVPort into a group (see example below)
>
>   def M7UnitVPort0 : ProcResource<1> { let BufferSize = 0; }
>   def M7UnitVPort1 : ProcResource<1> { let BufferSize = 0; }
>   
>   def M7UnitVPort : ProcResGroup<[M7UnitVPort0, M7UnitVPort1]>;
>
> At that point, you simply enumerate the resource units in the list of consumed resources. So, something like this:
>
> Example - before:
>
>   def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]>
>
> Example - after:
>
>   def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort0, M7UnitVPort1]>
>
> In conclusion, if the goal is to be able to do something like that, then I think the syntax is already expressive enough.
> The obvious downside is that currently you need to declare multiple resources to do what you want to do.

Unfortunately, I have tried doing this with a resource group with no success.  ExpandProcResources ends up marking the resource group as used for multiple cycles:

>From CortexM7ModelSchedClasses:

  {DBGFIELD("IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL") 1, true, false, 161, 4, 795, 1, 132, 3}, // #136

>From ARMWriteProcResTable:

  { 9,  1}, // #161
  {10,  2}, // #162
  {11,  1}, // #163
  {12,  1}, // #164

>From CortexM7ModelProcResources:

  {"M7UnitVFP",       1, 0, 0, nullptr}, // #9
  {"M7UnitVPort",     2, 0, 0, CortexM7ModelProcResourceSubUnits + 1}, // #10
  {"M7UnitVPort0",    1, 0, 0, nullptr}, // #11
  {"M7UnitVPort1",    1, 0, 0, nullptr}, // #12

In the end, the test in lines 1139-1140 of SubTargetEmitter.cpp forces multiple uses of a resource -- whether they be explicitly stated in an InstRW, implied by using different resources in a resource group, or hierarchically stated as using subunits of the resource -- to take multiple cycles.  That test seems so fundamental to the way that current schedule descriptions work that it seemed better to introduce the additional Uses notation than to change it.


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https://reviews.llvm.org/D94604



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