[PATCH] D94149: [RISCV] Add a partial test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results.

[Craig Topper via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2c51bef76cbf: [RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D94149?vs=314784&id=317391#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94149/new/

https://reviews.llvm.org/D94149

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll


Index: llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v25, v17, zero
+; CHECK-NEXT:    vadd.vv v26, v16, v17
+; CHECK-NEXT:    vmslt.vv v27, v26, v16
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v25, v27
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmerge.vim v16, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
+  %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
+  ret <vscale x 2 x i32> %d
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6602,7 +6602,7 @@
     EVT OverflowVT = MVT::i1;
     if (ResultVT.isVector())
       OverflowVT = EVT::getVectorVT(
-          *Context, OverflowVT, ResultVT.getVectorNumElements());
+          *Context, OverflowVT, ResultVT.getVectorElementCount());
 
     SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT);
     setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));


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