[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (WIP)

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I only looked at the ARM equivalent. From what I remember, the sequence of events was something like:

- One of the two operands to the mul was converted from a sext to an anyext. The other was not due to having multiple uses.
- That anyext was folded into a load to produce a zextload (we don't produce a vector anyext load)
- We couldn't match anything due one operand being a sext and the other being a zextload.

So in that case we would either need to use demanded bits know the top bits are not needed when converting it to a mull, create an anyextload instead of a zextload or handle multiple uses so both inputs turn into anyext or zextloads.

I'm happy for the isSignExtended change, as far as I understand that should be fine. The ARM side may be harder to fix, and as the test seems to only added for correctness - it doesn't seem like something that should hold up this patch. We should have fixed the majority of cases and if more come up we can tackle them as needed. I would be happy with this patch so long as the X86 changes are OK.


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