[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/lowerMUL-newload.ll:363
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    mla v0.4s, v1.4s, v3.4s
 ; CHECK-NEXT:    saddw v0.4s, v0.4s, v2.4h
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@dmgreen What do you think is the best way to extend D93833 to handle multiply-add/sub as well? Handle in DAG or refactor the isel patterns to accept sanyext/zanyext (I didn't get very far with my initial attempt with this approach as a lot of the patfrags were hardcodded)?


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  https://reviews.llvm.org/D56387/new/

https://reviews.llvm.org/D56387