[llvm] 911961c - [AMDGPU][MC][GFX10] Improved dpp8 errors handling
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 18 04:02:57 PST 2021
Author: Dmitry Preobrazhensky
Date: 2021-01-18T15:02:31+03:00
New Revision: 911961c9c1320ba985ac06c1866b33a5a247a94e
URL: https://github.com/llvm/llvm-project/commit/911961c9c1320ba985ac06c1866b33a5a247a94e
DIFF: https://github.com/llvm/llvm-project/commit/911961c9c1320ba985ac06c1866b33a5a247a94e.diff
LOG: [AMDGPU][MC][GFX10] Improved dpp8 errors handling
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D94756
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e73cf2f55ef2..99e7c0e2d6b8 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7260,25 +7260,23 @@ OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
int64_t Sels[8];
- if (!trySkipToken(AsmToken::LBrac))
+ if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
return MatchOperand_ParseFail;
- if (getParser().parseAbsoluteExpression(Sels[0]))
- return MatchOperand_ParseFail;
- if (0 > Sels[0] || 7 < Sels[0])
- return MatchOperand_ParseFail;
-
- for (size_t i = 1; i < 8; ++i) {
- if (!trySkipToken(AsmToken::Comma))
+ for (size_t i = 0; i < 8; ++i) {
+ if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
return MatchOperand_ParseFail;
+ SMLoc Loc = getLoc();
if (getParser().parseAbsoluteExpression(Sels[i]))
return MatchOperand_ParseFail;
- if (0 > Sels[i] || 7 < Sels[i])
+ if (0 > Sels[i] || 7 < Sels[i]) {
+ Error(Loc, "expected a 3-bit value");
return MatchOperand_ParseFail;
+ }
}
- if (!trySkipToken(AsmToken::RBrac))
+ if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
return MatchOperand_ParseFail;
unsigned DPP8 = 0;
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 7f77a0da2a78..ae8e95105c33 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -115,6 +115,19 @@ s_atomic_swap s5, s[2:3], 0x1FFFFF
// CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
// CHECK-NEXT:{{^}} ^
+//==============================================================================
+// expected a 3-bit value
+
+v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
//==============================================================================
// expected a 5-character mask
@@ -192,6 +205,11 @@ v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK: error: expected a closing square bracket
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK-NEXT:{{^}} ^
+
//==============================================================================
// expected a colon
@@ -228,6 +246,11 @@ v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK: error: expected a comma
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK-NEXT:{{^}} ^
+
//==============================================================================
// expected a comma or a closing parenthesis
@@ -351,6 +374,11 @@ tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK: error: expected absolute expression
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
//==============================================================================
// expected a message name or an absolute expression
@@ -383,6 +411,14 @@ ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
// CHECK-NEXT:{{^}} ^
+//==============================================================================
+// expected a hwreg macro or an absolute expression
+
+s_setreg_b32 undef, s2
+// CHECK: error: expected a hwreg macro or an absolute expression
+// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
+// CHECK-NEXT:{{^}} ^
+
//==============================================================================
// expected an 11-bit unsigned offset
@@ -415,12 +451,12 @@ v_mov_b32_sdwa v1, sext(u)
// CHECK-NEXT:{{^}} ^
//==============================================================================
-// expected a hwreg macro or an absolute expression
+// expected an opening square bracket
-s_setreg_b32 undef, s2
-// CHECK: error: expected a hwreg macro or an absolute expression
-// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
-// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
+// CHECK: error: expected an opening square bracket
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
+// CHECK-NEXT:{{^}} ^
//==============================================================================
// expected an operation name or an absolute expression
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