[PATCH] D88569: [DAGCombiner] Call SimplifyDemandedBits to simplify EXTRACT_VECTOR_ELT

Mon Jan 18 03:40:28 PST 2021

foad added inline comments.

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Comment at: llvm/test/CodeGen/X86/buildvec-insertvec.ll:783
   %5 = insertelement <4 x i32> undef, i32 %3, i32 undef
   store i32 %4, i32* undef
   ret <4 x i32> %5
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foad wrote:
> RKSimon wrote:
> > this should simplify to "store i32 undef, store i32* undef" and be removed - can you check why it isn't please?
> The value being stored is not undef, it's either -2147483648 or poison, depending on the value of %a0.
> 
> Anyway -simplifycfg would change the store into a trap + unreachable, but nothing in llc's codegen pipeline does that.
I've looked into this more carefully now. Hopefully this answer makes more sense.

With my patch `%4 = extractelement <4 x i32> zeroinitializer, i32 %2` is simplified into `i32 0` based on the known bits of all elements. This happens before we simplify %2, because of the weird way that the DAG combiner runs top-down.

When we visit %2 we simplify it to -2147483648. After that, if we visited the original %4 again, we would simplify it to undef; but with my patch we have already simplified %4 to 0 so it's too late.

I'm not sure what to do about this -- other than change DAGCombine to run bottom-up ;-)

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88569/new/

https://reviews.llvm.org/D88569