[PATCH] D94863: [RISCV] Implement vssseg intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 317291.
HsiangKai added a comment.

Add test cases for floating point types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94863/new/

https://reviews.llvm.org/D94863

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vssseg.ll

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