[PATCH] D94867: [ARM] Make a BE predicate bitcast consistent with the rest of llvm

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

In D94867#2504155 <https://reviews.llvm.org/D94867#2504155>, @markus wrote:

>> We were storing predicate registers, such as a <8 x i1>, in the opposite order to how the rest of llvm expects.
>
> It should be mentioned that it is, at least to me, unclear what llvm expects wrt this and as far as I know it is not documented anywhere. Simple experiment suggest that bit order is reversed for big endian targets
>
>   define i8 @foo() {
>   entry:
>     %v = insertelement <8 x i1> zeroinitializer, i1 true, i8 0
>     %bc = bitcast <8 x i1> %v to i8
>     ret i8 %bc
>   }
>
>   $ llc -O3 bitcast.ll --mtriple arm -o -     # lsb is set in scalar
>   $ llc -O3 bitcast.ll --mtriple armeb -o -     # msb is set in scalar
>
> with similar results for mips (big-endian) and amd64 (little-endian).

Yes, but that is base ARM and it is only MVE that is incorrect. You can see here that things were inconsistent, which is what this patch is fixing:
https://godbolt.org/z/M8Y6dv

> So before we go ahead an commit anything this should probably be clarified. I tried raising the issue on llvm-dev without much definitive response https://lists.llvm.org/pipermail/llvm-dev/2021-January/147725.html

It comes from https://reviews.llvm.org/D42100#992315. This patch just brings MVE inline with what the rest of llvm expects.


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