[PATCH] D94566: [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG383b6501ffed: [RISCV] Use tail agnostic policy for instructions with tied defs if the use… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D94566?vs=316272&id=317273#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94566/new/

https://reviews.llvm.org/D94566

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll


Index: llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
@@ -828,3 +828,20 @@
 
   ret <vscale x 8 x double> %a
 }
+
+; Test with undef for the dest operand. This should use tail agnostic policy.
+define <vscale x 1 x i8> @intrinsic_vcompress_um_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vcompress.vm v25, v16, v0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+  ret <vscale x 1 x i8> %a
+}
Index: llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
@@ -738,3 +738,21 @@
 
   ret <vscale x 8 x double> %a
 }
+
+; Test with undef for the dest operand. This should use tail agnostic policy.
+define <vscale x 1 x i8> @intrinsic_vcompress_um_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vcompress.vm v25, v16, v0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2319,8 +2319,15 @@
   // FIXME: This is conservatively correct, but we might want to detect that
   // the input is undefined.
   bool TailAgnostic = true;
-  if (MI.isRegTiedToUseOperand(0) && !WritesElement0)
+  unsigned UseOpIdx;
+  if (MI.isRegTiedToUseOperand(0, &UseOpIdx) && !WritesElement0) {
     TailAgnostic = false;
+    // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+    const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
+    MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg());
+    if (UseMI && UseMI->isImplicitDef())
+      TailAgnostic = true;
+  }
 
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth,


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