[PATCH] D94867: [ARM] Make a BE predicate bitcast consistent with the rest of llvm

[Markus Lavin via Phabricator via llvm-commits]

markus added a comment.

> We were storing predicate registers, such as a <8 x i1>, in the opposite order to how the rest of llvm expects.

It should be mentioned that it is, at least to me, unclear what llvm expects wrt this and as far as I know it is not documented anywhere. Simple experiment suggest that bit order is reversed for big endian targets

  define i8 @foo() {
  entry:
    %v = insertelement <8 x i1> zeroinitializer, i1 true, i8 0
    %bc = bitcast <8 x i1> %v to i8
    ret i8 %bc
  }

  $ llc -O3 bitcast.ll --mtriple arm -o -     # lsb is set in scalar
  $ llc -O3 bitcast.ll --mtriple armeb -o -     # msb is set in scalar

with similar results for mips (big-endian) and amd64 (little-endian).

So before we go ahead an commit anything this should probably be clarified. I tried raising the issue on llvm-dev without much definitive response https://lists.llvm.org/pipermail/llvm-dev/2021-January/147725.html


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