[PATCH] D94894: [RISCV] Add way to mark CompressPats that should only be used for compressing.

[Craig Topper via Phabricator via llvm-commits]

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There can be muliple patterns that map to the same compressed
instruction. Reversing those leads to multiple ways to uncompress
an instruction, but its not easily controllable which one will
be chosen by the tablegen backend.

This patch adds a flag to mark patterns that should only be used
for compressing. This allows us to leave one canonical pattern
for uncompressing.

The obvious benefit of this is getting c.mv to uncompress to
the addi patern that is aliased to the mv pseudoinstruction. For
the add/and/or/xor/li patterns it just removes some unreachable
code from the generated code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94894

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/TableGen/AsmPredicateCombiningRISCV.td
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

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