[PATCH] D94711: [PowerPC] Fix the check for the instruction using FRSP/XSRSP output register

[Victor Huang via Phabricator via llvm-commits]

NeHuang updated this revision to Diff 317105.
NeHuang added a comment.

Thanks @nemanjai. Test case added.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94711/new/

https://reviews.llvm.org/D94711

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll


Index: llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+
+define dso_local void @test(float* %Fptr, <4 x float>* %Vptr) local_unnamed_addr !dbg !8 {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:          addis 5, 2, .LCPI0_0 at toc@ha
+; CHECK-NEXT:          lfs 0, 0(3)
+; CHECK-NEXT:          addis 3, 2, .LCPI0_1 at toc@ha
+; CHECK-NEXT:          lfs 1, .LCPI0_0 at toc@l(5)
+; CHECK-NEXT:          lfd 2, .LCPI0_1 at toc@l(3)
+; CHECK-NEXT:          li 3, 0
+; CHECK-NEXT:          fsub 1, 1, 0
+; CHECK-NEXT:          stfs 0, 12(4)
+; CHECK-NEXT:          fadd 0, 1, 2
+; CHECK-NEXT:          frsp 0, 0
+; CHECK-NEXT:          #DEBUG_VALUE: test:Val <- $f0
+; CHECK-NEXT:          std 3, 4(4)
+; CHECK-NEXT:          stfs 0, 0(4)
+; CHECK-NEXT:          blr
+entry:
+  %0 = load float, float* %Fptr, align 4
+  %conv = fpext float %0 to double
+  %sub = fsub double 1.000000e+00, %conv
+  %sub1 = fadd double %sub, -4.300000e+00
+  %conv2 = fptrunc double %sub1 to float
+  call void @llvm.dbg.value(metadata float %conv2, metadata !19, metadata !DIExpression()), !dbg !20
+  %vecinit4 = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float poison>, float %conv2, i32 0
+  %vecinit5 = insertelement <4 x float> %vecinit4, float %0, i32 3
+  store <4 x float> %vecinit5, <4 x float>* %Vptr, align 16
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!6, !7}
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "XL C/C++ for Linux on Power, (IBM Internal Development Branch), clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "test.c", directory: "llvm-project/llvm")
+!2 = !{}
+!3 = !{!4, !5}
+!4 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+!5 = !DIBasicType(name: "double", size: 64, encoding: DW_ATE_float)
+!6 = !{i32 2, !"Debug Info Version", i32 3}
+!7 = !{i32 1, !"wchar_size", i32 4}
+!8 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !9, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
+!9 = !DISubroutineType(types: !10)
+!10 = !{null, !11, !12}
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 64)
+!13 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 128, flags: DIFlagVector, elements: !14)
+!14 = !{!15}
+!15 = !DISubrange(count: 4)
+!16 = !{!17, !18, !19}
+!17 = !DILocalVariable(name: "Fptr", arg: 1, scope: !8, file: !1, line: 1, type: !11)
+!18 = !DILocalVariable(name: "Vptr", arg: 2, scope: !8, file: !1, line: 1, type: !12)
+!19 = !DILocalVariable(name: "Val", scope: !8, file: !1, line: 2, type: !4)
+!20 = !DILocation(line: 0, scope: !8)
Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -712,7 +712,7 @@
               Simplified = true;
               Register ConvReg1 = RoundInstr->getOperand(1).getReg();
               Register FRSPDefines = RoundInstr->getOperand(0).getReg();
-              MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
+              MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines));
               for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
                 if (Use.getOperand(i).isReg() &&
                     Use.getOperand(i).getReg() == FRSPDefines)


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