[PATCH] D94818: [RISCV] Add zext.h instruction to Zbb.

[Craig Topper via Phabricator via llvm-commits]

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This uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.

I've added two new instructions with these specific encodings with
predicates that only enable them when Zbp isn't enabled. I've done
this for both the assembler/disassembler and codegen.

My goal here was to make zext.h be treated as an alias
for pack(w) when Zbb is enabled, prevent disassembling of the
illegal encodings when Zbp isn't enabled, and not accept the
pack spelling in the assembler without Zbp.

Similar will need to be done for rev8 and gorc.b that use specific
immediates of the general grevi/gorci encodings.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94818

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbb.ll
  llvm/test/CodeGen/RISCV/rv64Zbb.ll
  llvm/test/MC/RISCV/rv32zbb-valid.s
  llvm/test/MC/RISCV/rv64zbb-valid.s

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