[llvm] a0770f9 - [ARM] Constant tripcount tail predication loop tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 15 10:02:42 PST 2021
Author: David Green
Date: 2021-01-15T18:02:07Z
New Revision: a0770f9e4e923292066dd095cf01a28671e40ad6
URL: https://github.com/llvm/llvm-project/commit/a0770f9e4e923292066dd095cf01a28671e40ad6
DIFF: https://github.com/llvm/llvm-project/commit/a0770f9e4e923292066dd095cf01a28671e40ad6.diff
LOG: [ARM] Constant tripcount tail predication loop tests. NFC
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll
new file mode 100644
index 000000000000..480680bee89d
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll
@@ -0,0 +1,277 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s
+
+define dso_local i32 @test_500_504(i32* nocapture readonly %x) {
+; CHECK-LABEL: test_500_504:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: mov.w lr, #126
+; CHECK-NEXT: adr r2, .LCPI0_0
+; CHECK-NEXT: vldrw.u32 q0, [r2]
+; CHECK-NEXT: mov.w r2, #500
+; CHECK-NEXT: dls lr, lr
+; CHECK-NEXT: vdup.32 q1, r2
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: .LBB0_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vadd.i32 q2, q0, r1
+; CHECK-NEXT: vdup.32 q3, r1
+; CHECK-NEXT: vcmp.u32 hi, q3, q2
+; CHECK-NEXT: adds r1, #4
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsttt
+; CHECK-NEXT: vcmpt.u32 hi, q1, q2
+; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
+; CHECK-NEXT: vaddvat.u32 r2, q2
+; CHECK-NEXT: le lr, .LBB0_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: .LCPI0_0:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 1 @ 0x1
+; CHECK-NEXT: .long 2 @ 0x2
+; CHECK-NEXT: .long 3 @ 0x3
+entry:
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %entry
+ %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+ %vec.phi = phi i32 [ 0, %entry ], [ %4, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 500)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
+ %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
+ %3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
+ %4 = add i32 %3, %vec.phi
+ %index.next = add i32 %index, 4
+ %5 = icmp eq i32 %index.next, 504
+ br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body
+ ret i32 %4
+}
+
+define dso_local i32 @test_501_504(i32* nocapture readonly %x) {
+; CHECK-LABEL: test_501_504:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: adr r2, .LCPI1_0
+; CHECK-NEXT: mov.w lr, #126
+; CHECK-NEXT: vldrw.u32 q0, [r2]
+; CHECK-NEXT: adr r2, .LCPI1_1
+; CHECK-NEXT: vldrw.u32 q1, [r2]
+; CHECK-NEXT: dls lr, lr
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: .LBB1_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vadd.i32 q2, q0, r1
+; CHECK-NEXT: vdup.32 q3, r1
+; CHECK-NEXT: vcmp.u32 hi, q3, q2
+; CHECK-NEXT: adds r1, #4
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsttt
+; CHECK-NEXT: vcmpt.u32 hi, q1, q2
+; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
+; CHECK-NEXT: vaddvat.u32 r2, q2
+; CHECK-NEXT: le lr, .LBB1_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: .LCPI1_0:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 1 @ 0x1
+; CHECK-NEXT: .long 2 @ 0x2
+; CHECK-NEXT: .long 3 @ 0x3
+; CHECK-NEXT: .LCPI1_1:
+; CHECK-NEXT: .long 501 @ 0x1f5
+; CHECK-NEXT: .long 501 @ 0x1f5
+; CHECK-NEXT: .long 501 @ 0x1f5
+; CHECK-NEXT: .long 501 @ 0x1f5
+entry:
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %entry
+ %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+ %vec.phi = phi i32 [ 0, %entry ], [ %4, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 501)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
+ %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
+ %3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
+ %4 = add i32 %3, %vec.phi
+ %index.next = add i32 %index, 4
+ %5 = icmp eq i32 %index.next, 504
+ br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body
+ ret i32 %4
+}
+
+define dso_local i32 @test_502_504(i32* nocapture readonly %x) {
+; CHECK-LABEL: test_502_504:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: adr r2, .LCPI2_0
+; CHECK-NEXT: mov.w lr, #126
+; CHECK-NEXT: vldrw.u32 q0, [r2]
+; CHECK-NEXT: adr r2, .LCPI2_1
+; CHECK-NEXT: vldrw.u32 q1, [r2]
+; CHECK-NEXT: dls lr, lr
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: .LBB2_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vadd.i32 q2, q0, r1
+; CHECK-NEXT: vdup.32 q3, r1
+; CHECK-NEXT: vcmp.u32 hi, q3, q2
+; CHECK-NEXT: adds r1, #4
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsttt
+; CHECK-NEXT: vcmpt.u32 hi, q1, q2
+; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
+; CHECK-NEXT: vaddvat.u32 r2, q2
+; CHECK-NEXT: le lr, .LBB2_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: .LCPI2_0:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 1 @ 0x1
+; CHECK-NEXT: .long 2 @ 0x2
+; CHECK-NEXT: .long 3 @ 0x3
+; CHECK-NEXT: .LCPI2_1:
+; CHECK-NEXT: .long 502 @ 0x1f6
+; CHECK-NEXT: .long 502 @ 0x1f6
+; CHECK-NEXT: .long 502 @ 0x1f6
+; CHECK-NEXT: .long 502 @ 0x1f6
+entry:
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %entry
+ %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+ %vec.phi = phi i32 [ 0, %entry ], [ %4, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 502)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
+ %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
+ %3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
+ %4 = add i32 %3, %vec.phi
+ %index.next = add i32 %index, 4
+ %5 = icmp eq i32 %index.next, 504
+ br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body
+ ret i32 %4
+}
+
+define dso_local i32 @test_503_504(i32* nocapture readonly %x) {
+; CHECK-LABEL: test_503_504:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: movw r1, #503
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: dlstp.32 lr, r1
+; CHECK-NEXT: .LBB3_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vldrw.u32 q0, [r0], #16
+; CHECK-NEXT: vaddva.u32 r2, q0
+; CHECK-NEXT: letp lr, .LBB3_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %entry
+ %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+ %vec.phi = phi i32 [ 0, %entry ], [ %4, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 503)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
+ %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
+ %3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
+ %4 = add i32 %3, %vec.phi
+ %index.next = add i32 %index, 4
+ %5 = icmp eq i32 %index.next, 504
+ br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body
+ ret i32 %4
+}
+
+define dso_local i32 @test_504_504(i32* nocapture readonly %x) {
+; CHECK-LABEL: test_504_504:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: mov.w lr, #126
+; CHECK-NEXT: adr r2, .LCPI4_0
+; CHECK-NEXT: vldrw.u32 q0, [r2]
+; CHECK-NEXT: mov.w r2, #504
+; CHECK-NEXT: dls lr, lr
+; CHECK-NEXT: vdup.32 q1, r2
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: .LBB4_1: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vadd.i32 q2, q0, r1
+; CHECK-NEXT: vdup.32 q3, r1
+; CHECK-NEXT: vcmp.u32 hi, q3, q2
+; CHECK-NEXT: adds r1, #4
+; CHECK-NEXT: vpnot
+; CHECK-NEXT: vpsttt
+; CHECK-NEXT: vcmpt.u32 hi, q1, q2
+; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
+; CHECK-NEXT: vaddvat.u32 r2, q2
+; CHECK-NEXT: le lr, .LBB4_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: .LCPI4_0:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 1 @ 0x1
+; CHECK-NEXT: .long 2 @ 0x2
+; CHECK-NEXT: .long 3 @ 0x3
+entry:
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %entry
+ %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+ %vec.phi = phi i32 [ 0, %entry ], [ %4, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 504)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
+ %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
+ %3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
+ %4 = add i32 %3, %vec.phi
+ %index.next = add i32 %index, 4
+ %5 = icmp eq i32 %index.next, 504
+ br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body
+ ret i32 %4
+}
+
+declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
+declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
+declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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