[PATCH] D94730: [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.

[Sam Elliott via Phabricator via llvm-commits]

lenary added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1853
   }
+  case ISD::SETCC: {
+    // (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
----------------
Is this not a general purpose combine if you have the same boolean contents? Or does it hinder optimisations on other platforms with a wider variety of condition codes?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94730/new/

https://reviews.llvm.org/D94730