[PATCH] D94589: [RISCV] Add intrinsics for vector AMO instructions

[Zakk Chen via Phabricator via llvm-commits]

khchen added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:107
+}
+
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
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vlxe and vlse have the same logic and I think they can reuse above utility functions, right?
Do you have a plan to update them (vlxe and vlse) and make the same logic with consistent implementation?  maybe it could be in another patch.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:3228
+  defm "" : VPatAMOV_WD<"int_riscv_vamoswap", "PseudoVAMOSWAP", AllFloatVectors>;
+} // Predicates = [HasStdExtZvamo, HasStdExtF]
 
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Should it have HasStdExtV predicate?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94589/new/

https://reviews.llvm.org/D94589