[PATCH] D94294: [RISCV] Add scalable vector vselect ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:351
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
+                                                      vti.RegClass:$rs2)),
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rogfer01 wrote:
> rogfer01 wrote:
> > This is a heads up of an issue we may find by using `VMV0` here: this register class is a singleton and regalloc may fail in some cases because virtual registers of `VMV0` and further constrained classes built during codegen (such as `VR_and_VMV0`) only have one physical register `v0`.
> > 
> > I will try to create a smaller reproducer. For the time being, an example of what I'm seeing:
> > 
> > ```
> > %1047:vr_and_vmv0 = PseudoVMOR_MM_MF8 %1042:vr_and_vmv0, %1046:vr_and_vmv0, $noreg, -1, implicit $vl, implicit $vtype,
> > ```
> > 
> > It does not seem possible to have a possible for a register class that is the intersection of `VR` and `VMV0` (as it will only contain `v0`).
> > 
> > Perhaps we can teach the passes that constraint RCs (MachineCSE comes to mind but perhaps there are others) to refrain to do so when the restricted class would be a singleton.
> > 
> > I wonder if in the whole hierarchy of register classes, built using tablegen, we should avoid creating singletons in the first place (though there might be cases where this is useful?).
> > 
> > Thoughts?
> > It does not seem possible to have a possible for a 
> 
> It does not seem possible to have a valid allocation for a
Thanks for bringing this up. I was wondering if/when this would become a problem. I don't have any thoughts right now, but I wanted to add that I don't think this is strictly a problem with singletons, since you could have an intersection of only two registers but need three to satisfy an instruction. It just so happens that V0 is going to be the main sticking point for RVV. I bring this up in the context of teaching the passes to solve this, as I don't think that'll be possible in general.


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https://reviews.llvm.org/D94294