[PATCH] D94294: [RISCV] Add scalable vector vselect ISel patterns

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:351
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
+                                                      vti.RegClass:$rs2)),
----------------
This is a heads up of an issue we may find by using `VMV0` here: this register class is a singleton and regalloc may fail in some cases because virtual registers of `VMV0` and further constrained classes built during codegen (such as `VR_and_VMV0`) only have one physical register `v0`.

I will try to create a smaller reproducer. For the time being, an example of what I'm seeing:

```
%1047:vr_and_vmv0 = PseudoVMOR_MM_MF8 %1042:vr_and_vmv0, %1046:vr_and_vmv0, $noreg, -1, implicit $vl, implicit $vtype,
```

It does not seem possible to have a possible for a register class that is the intersection of `VR` and `VMV0` (as it will only contain `v0`).

Perhaps we can teach the passes that constraint RCs (MachineCSE comes to mind but perhaps there are others) to refrain to do so when the restricted class would be a singleton.

I wonder if in the whole hierarchy of register classes, built using tablegen, we should avoid creating singletons in the first place (though there might be cases where this is useful?).

Thoughts?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94294/new/

https://reviews.llvm.org/D94294