[PATCH] D94751: [RISCV] Correct alignment settings for vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

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According to "9. Vector Memory Alignment Constraints" in V specification, the alignment of vector memory access is aligned to the size of the element. In our current implementation, we support ELEN up to 64. We could assume the alignment of vector registers is 64 under the assumption.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94751

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -386,11 +386,10 @@
 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
   : RegisterClass<"RISCV",
                   regTypes,
-                  // FIXME: Spill alignment set to 16 bytes.
-                  128,
+                  64, // The maximum supported ELEN is 64.
                   regList> {
   int VLMul = Vlmul;
-  int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64
+  int Size = !mul(Vlmul, 64);
 }
 
 def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t,


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