[PATCH] D94711: [PowerPC] Fix the check for the instruction using FRSP/XSRSP output register

[Victor Huang via Phabricator via llvm-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, lei, stefanp, bsaleil, power-llvm-team.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, hiraditya.
NeHuang requested review of this revision.
Herald added a subscriber: llvm-commits.

When performing peephole optimization to simplify the code,  after removing passed FPSP/XSRSP instruction we will set any uses of that FRSP/XSRSP to the source of the FRSP/XSRSP.

We are finding the machine instruction using virtual register holding FRSP/XSRSP results by searching all following instructions. We are encountering an issue that the first use of the virtual register is a debug MI causing two issues

- virtual register in the debug MI removed unexpectedly
- virtual register used in non-debug MI not replaced with the source of FRSP/XSRSP. which stays in a undef status.

This patch fix the issue by only searching non-debug machine instruction using virtual register holding FRSP/XSRSP results


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94711

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp


Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -712,7 +712,7 @@
               Simplified = true;
               Register ConvReg1 = RoundInstr->getOperand(1).getReg();
               Register FRSPDefines = RoundInstr->getOperand(0).getReg();
-              MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
+              MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines));
               for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
                 if (Use.getOperand(i).isReg() &&
                     Use.getOperand(i).getReg() == FRSPDefines)


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