[PATCH] D94155: [X86] Fix tile config register spill issue.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke updated this revision to Diff 316634.
LuoYuanke added a comment.

We also need check tile config register interference. Since we
don't model the config register we should check interference from the
ldtilecfg to each tile data register def.

        ldtilecfg
        /       \
      BB1      BB2
       /         \
      call       BB3
      /           \
  %1=tileload   %2=tilezero

We can start from the instruction of each tile def, and backward to
ldtilecfg. If there is any call instruction, and tile data register is
not preserved, we should insert ldtilecfg after the call instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94155/new/

https://reviews.llvm.org/D94155

Files:
  llvm/include/llvm/CodeGen/LiveIntervals.h
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86PreTileConfig.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/Target/X86/X86TileConfig.cpp
  llvm/test/CodeGen/X86/AMX/amx-across-func.ll
  llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
  llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/opt-pipeline.ll

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