[PATCH] D93639: [AArch64][SVE]Add cost model for vector reduce for scalable vector

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Thanks for the changes so far, I think the patch is nearly there now.



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1153-1155
+  case ISD::FMUL:
+  case ISD::MUL:
+    return LegalizationCost + 16;
----------------
SVE has no instructions for MUL/FMUL reductions, so these should fall under `default` (return Invalid).


================
Comment at: llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vector-reduce.ll:14
+
+  %r = call i64 @llvm.vector.reduce.add.nxv8i64(<vscale x 8 x i64> %v)
+  ret i64 %r
----------------
Can you make two tests for each reduction:
* One with a legal type (`<vscale x 2 x i64>` (or `<vscale x 2 x double>` for fp reductions))
* One with an illegal type that needs splitting (`<vscale x 8 x i64>` (or `<vscale x 8 x double>` for fp reductions))


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93639/new/

https://reviews.llvm.org/D93639