[PATCH] D94628: [RISCV] Add implementation of targetShrinkDemandeConstant to optimize AND immediates.

[Craig Topper via Phabricator via llvm-commits]

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SimplifyDemandedBits can remove set bits from immediates from instructions
like AND/OR/XOR/ADD/SUB. This can prevent them from being efficiently
codegened on RISCV.

This adds an initial version that tries to keep or form 12 bit
sign extended immediates for AND operations to enable use of ANDI.

More optimizations are possible for different size immediates or
different operations. But this is a good starting point that already
has test coverage.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94628

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/frame-info.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
  llvm/test/CodeGen/RISCV/vararg.ll

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