[PATCH] D94615: [RISCV][WIP] Add RVV insertelt/extractelt scalable-vector patterns

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 13 10:17:36 PST 2021


frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, evandro, rogfer01, HsiangKai.
Herald added subscribers: NickHung, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
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---

Tagged as WIP as there are already concerns about there being too many
patterns, so I'm not sure if this is the route we'll take. I'm therefore making
this patch available more to gather thoughts about the general codegen strategy
for these operations (especially the problem with RV32).

It also uses RISCVISD::VMV_X_S at one point, above which there's a comment
saying "The result size will never be less than the vector element size". I

haven't addressed that comment yet.
-----------------------------------

Original patch by @rogfer01.

This patch adds support for insertelt and extractelt operations on
scalable vectors.

Special care must be taken on RV32 when dealing with i64 vectors as
there are no straightforward ways to insert a 64-bit element without a
register of that size. To that end, both are custom-lowered to different
sequences.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94615

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

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