[PATCH] D94590: [RISCV] Add ISel patterns for scalable mask exts & truncs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:516
+                zero_splat, 1, (vti.Mask $rs1), VLMax, vti.SEW)>;
+  def : Pat<(vti.Mask (trunc (vti.Vector vti.RegClass:$rs1))),
+            (!cast<Instruction>("PseudoVMSNE_VI_"#vti.LMul.MX)
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trunc would probably be better custom lowered. We should be able to remove the AND if the input has enough 0 bits. Not sure if SimplifyDemandedBits is capable of that for scalable vectors yet.

sext/zext/anyext might also be better custom lowered just to cut down on patterns. Our isel table is approaching 1MB. The next largest target is at about 600K.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94590/new/

https://reviews.llvm.org/D94590