[PATCH] D94450: [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Looking good on the RISC-V side.

Would you mind removing the out-of-date TODOs? They were out of date before, but with this change they're even more out of date.



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Comment at: llvm/test/CodeGen/RISCV/double-br-fcmp.ll:308
 
 ; TODO: feq.s+sltiu+bne -> feq.s+beq
 define void @br_fcmp_one(double %a, double %b) nounwind {
----------------
Please can you remove this TODO, as it is no longer relevant?


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Comment at: llvm/test/CodeGen/RISCV/double-select-fcmp.ll:209
 define double @select_fcmp_one(double %a, double %b) nounwind {
 ; TODO: feq.s+sltiu+bne sequence could be optimised
 ; RV32IFD-LABEL: select_fcmp_one:
----------------
And here.


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Comment at: llvm/test/CodeGen/RISCV/float-br-fcmp.ll:285
 
 ; TODO: feq.s+sltiu+bne -> feq.s+beq
 define void @br_fcmp_one(float %a, float %b) nounwind {
----------------
and here


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Comment at: llvm/test/CodeGen/RISCV/float-select-fcmp.ll:168
 define float @select_fcmp_one(float %a, float %b) nounwind {
 ; TODO: feq.s+sltiu+bne sequence could be optimised
 ; RV32IF-LABEL: select_fcmp_one:
----------------
And this one


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Comment at: llvm/test/CodeGen/RISCV/half-br-fcmp.ll:261
 
 ; TODO: feq.h+sltiu+bne -> feq.h+beq
 define void @br_fcmp_one(half %a, half %b) nounwind {
----------------
And here!


================
Comment at: llvm/test/CodeGen/RISCV/half-select-fcmp.ll:138
 define half @select_fcmp_one(half %a, half %b) nounwind {
 ; TODO: feq.h+sltiu+bne sequence could be optimised
 ; RV32IZFH-LABEL: select_fcmp_one:
----------------
and here!


Repository:
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https://reviews.llvm.org/D94450